The Data and Machine Learning Innovation (DMLI) team employs ML/HW/SW co-design to achieve best-in-class performance and energy efficiency for numerous use cases that deploy neural networks. We seek a generalist to help define and implement features that would be realized in next-gen neural accelerators. Our team is comprised of HW, SW, and ML engineers working together in the area of Efficient ML. Our charter is to push the frontiers of perf and power for AI inference. As a co-design engineer, you will be accountable for bridging the gap between ML and devices. This including working with ML, computer architecture and SW teams to understand the trade-offs from various viewpoints when it comes to ML inference, keeping abreast of advancements in the ML efficiency techniques space particularly for Generative AI, and come up with novel solution that addresses the ever growing needs for the future ML workloads. On a day-to-day basis, your responsibilities include but not be limited to: architecting energy-efficient hardware designs, implementing changes in an in-house simulator, implementing new features in an in-house compiler and working with ML engineers to optimize their networks for HW acceleration. Our ideal team member is courageous when it comes to trying new things, is adept at reasoning about systems performance, and is willing to iterate on ideas. We value team members with strong communication skills with experience working cross-functionally with HW, SW, and ML teams.