Become part of a growing Analog design & development team in the area of High Speed Serdes Interfaces .

You will lead and develop Analog Full custom circuit macros, i.e. CTLE & Analog Front End, DFE , high Speed clock paths , low power biasing , PLL, Regulators, equalizers, needed for High Speed PHY IP,  in planer and fin-fet CMOS technology..

You will be working with experienced set of teams locally & with people from various sites spread across globe.

This role involves analyzing various mixed signal techniques for dynamic and static power reduction, performance enhancement and area reduction. You’d leverage your strong understanding of circuit simulation and circuit layout as well as knowledge of bipolar, CMOS, passive structure, and interconnect failure modes.

Key Qualification:
BE +10 years of relevant experience / MTech +8 years of relevant experience in Electrical/Electronics/VLSI Engineering or other relevant field of study.

Technical Attributes

Mandatory:
 CMOS circuit design fundamentals, device physics, basic understanding of layout and parasitic extraction, spice simulation, sub-micron design methodologies, PLL/DLL, Voltage Regulators, data converters, Equalizers, Impedance calibrators.Analog transistor level circuit design in nanometer technologies.Familiarity Multi Gbps range High speed designsCan micro architect circuit from specifications, can create simulation benches to verify the specification, can understand and debug circuit.Should have sound understanding of layout and parasitic extraction & reduction techniquesExpertise with spice simulations in addition to various sub-micron design methodologies. 
Preferred:Familiarity Multi Gbps range High speed designs and familiarity with such specs.Familiarity with designs of PLLs, Regulators, Equalizers, Impedance calibrators etc.Familiarity with automation / Scripting language