Analog Design, Sr Staff Engineer
Synopsys (formerly Synfora)
Sr. Staff Analog and Mixed Signal Design Engineer
Join us as an analog and mixed-signal design engineer in the PLL design team. Our designs enable the next generation of datacenters, automobiles and communications networks. You will work on system-level and circuit-level PLL design in the latest FINFET and gate all around CMOS technology nodes. PLL designs will support high-speed Serdes designs including PCI-Express, Ethernet, CPRI, and other applications at rates up to 112Gbps, 128Gbps, 224Gbps and beyond.
Responsibilities and Duties:Circuit-level PLL design and PLL top-level modeling and simulationDesign of analog circuits such as VCOs, charge pumps and voltage regulatorsCustom circuit design in deep-submicron and FINFET CMOS technologiesDesign of high-speed digital circuits such as dividers and clock distribution pathsSchematic entry and spice simulation of custom circuitsProvide mentoring and technical leadership to junior designersCoordinate and interface with layout and CAD teams
Qualifications and Experience:8+ years of experience within CMOS analog and mixed-signal circuit design with MSEE or PhD. Candidates with a Bachelor’s degree and additional experience will also be consideredDetailed knowledge of PLL loop operation and designExperienced in design of SerDes blocks and/or PLL circuit components such as VCO's, charge-pumps, regulators and high-speed dividers.Design experience in FINFET and gate-all-around CMOS technologiesHspice, Finesim, PrimeSim or similar spice-type simulatorsSchematic entry in Synopsys Custom Designer or similar toolsKnowledge of digital timing in PrimeTime and/or Nanotime is an asset
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Stay Connected: Join our Talent Community
Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.
Join us as an analog and mixed-signal design engineer in the PLL design team. Our designs enable the next generation of datacenters, automobiles and communications networks. You will work on system-level and circuit-level PLL design in the latest FINFET and gate all around CMOS technology nodes. PLL designs will support high-speed Serdes designs including PCI-Express, Ethernet, CPRI, and other applications at rates up to 112Gbps, 128Gbps, 224Gbps and beyond.
Responsibilities and Duties:Circuit-level PLL design and PLL top-level modeling and simulationDesign of analog circuits such as VCOs, charge pumps and voltage regulatorsCustom circuit design in deep-submicron and FINFET CMOS technologiesDesign of high-speed digital circuits such as dividers and clock distribution pathsSchematic entry and spice simulation of custom circuitsProvide mentoring and technical leadership to junior designersCoordinate and interface with layout and CAD teams
Qualifications and Experience:8+ years of experience within CMOS analog and mixed-signal circuit design with MSEE or PhD. Candidates with a Bachelor’s degree and additional experience will also be consideredDetailed knowledge of PLL loop operation and designExperienced in design of SerDes blocks and/or PLL circuit components such as VCO's, charge-pumps, regulators and high-speed dividers.Design experience in FINFET and gate-all-around CMOS technologiesHspice, Finesim, PrimeSim or similar spice-type simulatorsSchematic entry in Synopsys Custom Designer or similar toolsKnowledge of digital timing in PrimeTime and/or Nanotime is an asset
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Stay Connected: Join our Talent Community
Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.
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