The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, interface IP, security IP, embedded processors, and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP Prototyping Kits and IP subsystems. Our extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market. At Synopsys, you will have the opportunity to find the perfect blend of our exceptional EDA presence and our broad IP portfolio.
 
Our Solution IP group is ramping up high-performance computing (HPC) demand, therefore we are looking for an enthusiastic applicant to join our team. You will be working with a cross functional team of analog and mixed signal circuit designers from a wide variety of backgrounds on design and methodology. This position requires hands on experience with transistor level simulations, reliability analysis, static timing analysis (STA) tools, a vast knowledge of mixed signal circuit design principles, a deep understanding of silicon IP release requirements, strong scripting skills to automate flows and the ability to lead and train junior engineers to become experts with new methodologies.
 
Key Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or similar technical fieldBSEE degree and 12-15 years of experience in IC design, or MSEE (or PhD) with 10-12 years of experience.Extensive programming skills in languages such as Python, Perl, TCL and C/C++Ability to provide automation​ for rapid and dynamic design needs is highly sought-afterExtensive knowledge of Analog & Mixed-Signal circuit designDesign experience in high speed PHY such as DDR, HBM or SERDESProficiency with spice simulators including HSPICE, Finesim and XADeep knowledge on DC/AC/Transient, Cross corners PVT, Static & Dynamic CCK, Equivalency checks, Aging, EMIR/SHE Reliability analysis, MonteCarlo simulationsExperience with STA and cell characterization such as Nanotime, Primetime, SiliconSmartUnderstanding of behavioral Verilog models & experience in SystemVerilog for AMS circuits Knowledge in Perforce and/or regressions is a plusExposure and working knowledge preferably with Synopsys tools like DC, PT, PT-SI and ICC2Prior working knowledge in the DDR/SERDES PHY level timing closure, implementation would be an added advantageCandidate with Machine Learning paradigms/techniques understandings with knowledge of applying it in modeling, circuit design flow & simulations is desirable
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP: predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.


At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.