SerDes System Architect

You will be part of an R&D team developing 8 to 224Gbps and NRZ and PAM4 serial-link (SerDes) transceivers. We are looking for an engineer with theoretical knowledge and practical experience to join our team. You will work with a cross-functional team of analog and digital designers, and hardware engineers.

You will be involved in all stages of development including:Modelling: updating and maintaining SerDes system modelsSign-off: running system simulations to verify design performance across multiple protocols and channelsAlgorithms: proposing and designing algorithms to calibration and adapt the transceiver for optimal performanceSilicon: correlating simulated performance with silicon measurementsCustomers: assisting customers with system-level performance issues
You have an B.E/Btech/Mtech/MS/M.Sc. or Ph.D. in Electronics or Computer Engineering with 5 years or more experience in related area of expertise .

Due to the cross disciplinary nature of this position, key qualifications include one or more of the following:Modelling - experience modeling circuits and systems in MATLAB/SimulinkAnalog – experience designing high-speed analog CMOS circuitsDigital – experience with DSPCommunications theory – experience with equalization, coding, noise/crosstalk filtering
Beneficial Experience: Experience analyzing link budgets for NRZ and/or PAM4 high-speed serial linksExperience modelling of SERDES transmitters and receivers in MATLAB or similar toolKnowledge of circuit topologies used in high-speed SerDes Tx/RxKnowledge of Tx/Rx equalization techniquesKnowledge of CDR architectures and CDR loop dynamicsKnowledge of common high-speed serial data protocols including PCIe, 10G/25G/56G/112G Ethernet, JESD204C, CPRIExperience with lab tests for high-speed serial linksExperience with C/Verilog-A/systemVerilog
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