Applications Engineering, Staff Engineer
Sypnosis
Description:
As the SoC are getting complex and thus includes complex verification methodologies and challenges. To address these needs Synopsys Verification Continuum™ platform provides VCS® simulation, Verdi® debug, SpyGlass® static, VC Formal, fastest emulation system and Prototyping. Prototyping is one of the key solution as it enables verification with real world interface and enabling software development and helps to catch bugs found during system validation. Any bugs found in final ASICs involve re-spins which in turn involve huge cost and may miss the market opportunities for end products.
Synopsys’s HAPS Based Prototyping includes HAPS hardware and HAPS ProtoCompiler tools that provides design automation and debug for the HAPS Series of FPGA-based prototypes. Features include: FPGA synthesis for HAPS, system planning, RTL debug and system bring-up utilities.
World’s top chip design companies use our products to do SOC validation and software development of complex SoC whose end products are smart devices & phones, network devices, medical instrumentation, and many other products. In this job, the qualified candidates will get opportunity to work on best in class FPGA based prototyping products developed in Synopsys. You get unique opportunity not only to understand the key challenges that our customer face in FPGA prototyping but you get chance to work the latest technology that Synopsys develops to address these challenges.
Responsibilities
You will be working as Applications Engineer, Sr II in Synopsys, you will be responsible for pre-sale and post-sale support of Synopsys’s HAPS Based Prototyping. You will have the opportunity to work with customers to help successfully prototype their multi-million gate ASIC designs.
This job provides an opportunity for you to be involved in highly technically challenging evaluations of Synopsys’s HAPS Based Prototyping and Implementation Products. You will part of Product Application team who act as experts of our Prototyping products in Synopsys. The responsibility includes supporting Synopsys customers for various product evaluations and post sale support using CRM/Solvent systems. To help with Pre-sales activity or product deployments or support issues, you may be required to travel to work in customer sites for specific periods of time. You will be required to publish solvent articles and developing application notes based on customer experiences. You will be responsible for developing training materials required for the customers. You are also expected to contribute improving the Quality of Results in the tools and propose new flows and features.
Minimum Requirements
BS with minimum 5-6 years of relevant experience or MS with minimum 4-5 years of experience.
Preferred Skills
Experience on FPGA based prototyping/emulation of complex SoCs.
Good understanding of the issues involved in ASIC to FPGA RTL preparation.
Must have knowledge of Digital Design, VHDL/Verilog/SystemVerilog , Synthesis, Simulation and FPGA architectures such as Xilinx or Altera.
Expert in Static Timing Analysis.
Intermediate knowledge scripting language such as Perl/TCL/Shell
Knowledge of ARM buses, display controller/interface, industry standards (MIPI, HDMI, USB, PCIe, SATA etc.) is a plus
As the SoC are getting complex and thus includes complex verification methodologies and challenges. To address these needs Synopsys Verification Continuum™ platform provides VCS® simulation, Verdi® debug, SpyGlass® static, VC Formal, fastest emulation system and Prototyping. Prototyping is one of the key solution as it enables verification with real world interface and enabling software development and helps to catch bugs found during system validation. Any bugs found in final ASICs involve re-spins which in turn involve huge cost and may miss the market opportunities for end products.
Synopsys’s HAPS Based Prototyping includes HAPS hardware and HAPS ProtoCompiler tools that provides design automation and debug for the HAPS Series of FPGA-based prototypes. Features include: FPGA synthesis for HAPS, system planning, RTL debug and system bring-up utilities.
World’s top chip design companies use our products to do SOC validation and software development of complex SoC whose end products are smart devices & phones, network devices, medical instrumentation, and many other products. In this job, the qualified candidates will get opportunity to work on best in class FPGA based prototyping products developed in Synopsys. You get unique opportunity not only to understand the key challenges that our customer face in FPGA prototyping but you get chance to work the latest technology that Synopsys develops to address these challenges.
Responsibilities
You will be working as Applications Engineer, Sr II in Synopsys, you will be responsible for pre-sale and post-sale support of Synopsys’s HAPS Based Prototyping. You will have the opportunity to work with customers to help successfully prototype their multi-million gate ASIC designs.
This job provides an opportunity for you to be involved in highly technically challenging evaluations of Synopsys’s HAPS Based Prototyping and Implementation Products. You will part of Product Application team who act as experts of our Prototyping products in Synopsys. The responsibility includes supporting Synopsys customers for various product evaluations and post sale support using CRM/Solvent systems. To help with Pre-sales activity or product deployments or support issues, you may be required to travel to work in customer sites for specific periods of time. You will be required to publish solvent articles and developing application notes based on customer experiences. You will be responsible for developing training materials required for the customers. You are also expected to contribute improving the Quality of Results in the tools and propose new flows and features.
Minimum Requirements
BS with minimum 5-6 years of relevant experience or MS with minimum 4-5 years of experience.
Preferred Skills
Experience on FPGA based prototyping/emulation of complex SoCs.
Good understanding of the issues involved in ASIC to FPGA RTL preparation.
Must have knowledge of Digital Design, VHDL/Verilog/SystemVerilog , Synthesis, Simulation and FPGA architectures such as Xilinx or Altera.
Expert in Static Timing Analysis.
Intermediate knowledge scripting language such as Perl/TCL/Shell
Knowledge of ARM buses, display controller/interface, industry standards (MIPI, HDMI, USB, PCIe, SATA etc.) is a plus
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