Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco’s silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide.

What You'll Do

You will author design specifications and participate in micro-architecture specification reviews. Implement Verilog RTL to meet timing, performance, and power requirements Contribute to full chip integration and timing methodology / analysis Develop and analyze functional coverage. Collaborate with the verification team to address design bugs and close code coverage. Work closely with physical design team to close design timing and place-and-route issues. Triage, debug, and root cause simulation, software bring-up, and customer failures. Perform diagnostic and post silicon validation tests in the lab.

Who You'll Work With

You will work with exceptional talent with vast ASIC design and development expertise. 

With Cisco being a systems company, you will also have an opportunity to work with other ASIC teams in the journey of taking it from concept to first customer shipments.

Who you Are

Minimum Qualifications:

Bachelor’s or Master’s degree in Electrical or Computer engineering. 8+ years of ASIC Design experience. Excellent Verilog/System Verilog programming skills. Possesses interactive and waveform debug skills. Good written and verbal communication skills. Collaborative and team-focused with the commitment to learn and grow. Preferred Qualifications:Scripting experience (Python, Perl, TCL, shell programming)Experience with Synopsys Design Constraints (SDC)
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