SummaryPosted: Nov 13, 2024Role Number:200578958Do you love crafting elegant solutions to highly sophisticated challenges? As part of our Hardware Technologies group, you’ll help design our next-generation, high-performance, power-efficient system-on-chips (SoCs). You will ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices! In this highly transparent role, you will be at the center of the Pixel IP design effort to accelerate machine learning applications. You will collaborate with all teams, making a critical impact getting functional products to millions of customers quickly.DescriptionDescriptionAs an ASIC Design Engineer in the Pixel IP DMA team, you will work closely with architecture, design, and verification teams to build commitment and low power DMA engines. Apply your knowledge of flow control, arbitration, cache design, compression, pipelining, sequencers, and other techniques to coordinate moving large amounts of data between the memory subsystem and the Apple Neural Engine Core (ANE). In this front-end design role, your tasks will include: - Coding high-quality RTL, with embedded assertions and cover points. - Writing detailed micro-architectural specifications. - Collaborating with multi-functional teams to explore solutions that enhance performance while minimizing power and area. - Working closely with design verification and formal verification teams to debug and verify functionality and performance.Minimum QualificationsMinimum QualificationsBachelor's degree + 3 Years of ExperienceKey QualificationsKey QualificationsPreferred QualificationsPreferred QualificationsExperience in SoC front-end ASIC RTL digital logic design using Verilog, or System Verilog.Experience working multi-functionally with architecture, design, and verification teams to specify, design, and debug designs.Experience in front-end implementation tasks such as synthesis, timing, area/power analysis, linting, and logic equivalence checks.Good collaboration skills with strong written and verbal communication skills.Good understanding of flow control, arbitration, address translation, caching, on-chip interconnects, and performance analysis.Prefer previous experience designing dedication DMA engines, multimedia IPs (especially AI/ML applications), data storage, memory controllers, networking, image processing, interconnects, and/or low power design.Prefer familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB), and relevant scripting languages (Python, Perl, TCL).Education & ExperienceEducation & ExperienceAdditional RequirementsAdditional RequirementsPay & BenefitsPay & BenefitsAt Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $143,100 and $264,200, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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