You will get involved in the definition, architecture, design and verification of dedication ASICs on the latest technology nodes. You will be working with software and marketing teams to define the feature sets and architect the solutions. Work will include new designs from scratch as well as maintaining or enhancing existing designs. You will be responsible for defining the test plan and actively working with verification teams to deliver high-quality designs. Debug tests in simulation and emulation environments. You’ll also work actively with the physical design team to resolve implementation and timing issues.
This is primarily an opening for a design engineer but if you are proficient in both design and verification, then we have the ideal match. In the verification role, you will be responsible for defining the test plan, developing the verification environment, and defining and coding the test suites. You will be verifying at the block level as well as the full chip level, in simulation and emulation.
You will be working with multiple teams across geographies.
We are looking for motivated individuals, who have excellent analytical and problem-solving abilities, who are open and have the ability to assimilate new techniques and enjoy challenging tasks.
Who You Are Proficient in Verilog Have extensive experience in ASIC front-end ASIC design. Strong experience with synthesis, timing analysis and power analysis. Perl/Python/Makefiles scripting is strongly preferred Experience designing ASICs for networking protocols (Ethernet, FC) is a plus Must be strong at documenting the design specifications, verification plan and presentations Strong problem-solving and ASIC debugging skills Ability to debug system-wide issues