Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Principle RTL Design Engineer

Synopsys is seeking a talented RTL Design Engineer and an expert in microarchitecture, RTL development for our next-generation ARC-V processor IP. Synopsys ARC-V processors IP is based on the open-source standard RISC-V instruction set architecture. The ideal candidate is experienced in the microprocessor development process, resolution of critical problems, and has a consistent track record of delivering timely and high-quality products. Cutting edge experience in IP architecture and design, utilizing the latest process technologies, is preferred.

ResponsibilitiesWorking closely with architects to develop micro-architecture and hardware specifications for the design blocks for ARC-V processor IP.Developing RTL code for the design blocks with PPA considerationsCarrying out Linting, CDC, RDC, Synthesis and Timing Analysis of design blocksWork closely with verification team to review test plans and setting the sign-off criteria for the design and verification activitiesInteract and collaborate with various stake holders in the project (in areas related to Verification, SW, DFT, Physical design, Prototyping.. etc)Mentor other engineers
Qualifications / Skills DesiredBachelors of Science in Computer, Electrical Engineering or similarMinimum of 10 years experience in ASIC digital design domainOr Master of Science in Computer, Electrical Engineering or similarMinimum of 8 years experience in ASIC digital design domainTeam oriented person with clear verbal and written communicationExperienced in CPU/processor architectures; RISC-V experience highly desirableKnowledge of design techniques for high performance and low powerMust have strong digital design fundamentalsHands-on expertise with Verilog, System VerilogHands-on expertise with debugging failed scenarios using DVE/VerdiHands-on expertise with Spyglass, Design Compiler, TCM/FishtailExperience in developing scripts using Perl, Python, Javascript or similar languagesHands-on expertise debugging CPU designs is highly desirableExcellent debug and problem solving skillsExperience with git or other revision control environmentsExposure to automotive safety (ASIL) standards is an advantageThe base salary range across the U.S. for this role is between $172,000-$258,000 annually. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability