Job DescriptionsWork in a Digital and Verification Development team during the development and validation of complex digital mix signals for high-speed interface IP.Test planning, checklist, Coverage and Assertion planningHands on experience in creating detailed Verification Environment from Functional SpecificationsApplying advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification.Writing test cases, checkers, and coverage that implement the verification test plan.Debug of simulations, including those of real signals modeled using SV for analogRTL, GLS & Co-simulations & coverage closureParticipate in technical reviews and contribute activelyParticipate in customer support with bring-up of IP in customer simulation environmentFollow and improve development process ensuring high quality output.Skills RequirementsBS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications. 4+ years of experience in Design VerificationStrong skill with VCS/Verdi simulation tools, Formal verification tool (vc_formal)Knowledge of UPF, UVM(Universal Verification Methodology) and SVA (System-Verilog Assertion) is a plusStrong debug skills and demonstrated experiences in Perl /TCL/Python scripting is a plusHighly responsible, result orientedGood English communication both verbally and in writingGreat team player, willing to support othersSelf-motivated and highly enthusiasm in technology and solving problemsSynopsys delivers leading silicon to systems design solutions that maximize our customers’ R&D capability and productivity. Companies trust Synopsys to pioneer new technologies getting them to market faster without compromise.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.