Senior ASIC Design Engineer

You would be working as part of a highly experienced digital design team, targeting the next generation ARC processor IP. The ideal candidate is experienced in microprocessor development process and resolution of critical problems. The position offers an excellent opportunity to work with an experienced team of engineers involved in defining and implementing Functional Safety for all ARC Processor IPs.
 
Key QualificationsMSEE graduate plus minimum 1 year or BSEE graduate plus minimum 2 years of digital design experience in the industryMust have hands-on experience in RTL design(Verilog or System Verilog). Familiarity with Computer architecture conceptsMust have experience with CDC/RDC/LINT toolsHands-on expertise with debugging failed scenarios using DVE/VerdiScripting experience in one or more languages : Shell, Perl, Python Good organization and communication skills for interacting between different design groups Must be self-motivated, proactive, and able to balance good design quality while meeting tight deadlines
Preferred Qualifications / SkillsHands-on experience with multiple clock domain designScripting experience in Shell, Perl, Python and TCL is a plusFamiliarity with ISO 26262 standard is a huge plus RISC-V experience highly desirableExcellent debug and problem solving skillsExperience with GIT or other revision control environments