Job Description and Requirements 
 
Job Title: ASIC Digital Design, Staff Engineer
Location -INDIA - Bangalore 

Job Description 
 
The candidate will be part of the DesignWare IIP RTL Design team at Synopsys. He/She will be expected to specify, design/architect and implement state-of-the-art RTL designs for the DesignWare family of synthesizable cores. He/ She will work closely with other RTL designers and be part of a global team of  
expert Engineers. 
Job Responsibilities – 
 
You will be working as a Senior RTL Designer with the following responsibilities. 

Work on Architecture, RTL Design and ownership of High Definition VESA VDC-M-1.1/1.2 Video Codec products targeted towards AR/VR, MIPI DSI, HDMI 2.1 and DisplayPort Protocols Understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create architecture and micro-architecture with detailed design documents for some of the components of the design for medium to high complexity functionality. Be an individual contributor in the Design Tasks – Micro Architecture Design – propose various options for Area, Timing and throughput trade-offs, RTL coding of design, synthesis, CDC analysis, debug, Test development etc. May need to interact with customers to discuss/ understand customers’ specification requirements, if needed . Work in a project and team-oriented environment with teams spread across multiple sites, worldwide. Able to own the product from concept to delivery.  Key Qualifications and Experience- 
Must have BSEE or MSEE in EE with 5+ years of relevant experience in the following areas: 
 Hands on design of data path designs and algorithmic blocks such as VESA DSC-1.1/1.2 video codecs, H.263/H.264 Video codecs, Reed Solomon FEC encoder and Decoder as per IEEE 802.3-bj,ck,bs specifications, BCH codes, Parallel CRC computation architectures, MAC SEC engines.  Hands-on experience in translating the algorithm specification given in C/C++ to Micro architecture, RTL Design for area, latency, throughput trade-offs, Clock Domain Crossing Architectures  Knowledge of one or more of protocols/standards: VESA VDC-M, DSC, HDMI 2.1, MIPI DSI, AMBA (AXI,APB,AHB)  Experience with control path oriented designs like asynchronous FIFOs, SPRAM/ DPRAM interface design, and designs with multiple clocks involving various Clock Domain Crossing schemes. Hands on experience with architecting/ micro-architecture/ detailed design from Functional Specifications. Hands on experience with Synthesizable Verilog/ System Verilog RTL coding for ASIC designs and Simulation tools Hands on experience in writing self checking Verilog Testbenches to verify module level designs  Spyglass Lint, CDC, Design Compiler Synthesis flow and static timing flows, Formal checking, etc is a must for candidates with design background. Experience with high speed design greater than 800MHz and with P&R aware synthesis including usage of tools such as Fusion Compiler is a significant plus. Experience with Perforce or similar revision control environment Hands-on experience in TCL, Python scripting for automation. Exposure to quality processes in the context of IP design and verification is an added advantage.In addition, the candidate should have good communication skills, should be a team player and possess good problem solving skills and show high levels of initiative. 

This position requires prior industry experience and is not open for college fresh grads. 
  
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.