ASIC Digital Design, Senior Engineer 49262BR INDIA - Bangalore 
Job Description : At Synopsys, we are at the heart of the innovations that change the way we work and play. Selfdriving cars, Artificial Intelligence, The cloud, 5G, The Internet of Things, These breakthroughs are ushering in the Era of Smart Everything. And we are powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk. We are looking for ASIC Digital Design Verification engineer to work on VLSI IP verification of controllers related to complex protocols.  The candidate will be part of the Solutions Group at our Bangalore Design Center, India. The position offers learning and growth opportunities. This is a Senior Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in the Verification domain.
Job Responsibilities - Understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design for some of the components of the Test Environment for the DesignWare family of synthesizable cores in protocol areas such as AMBA (AMBA2, AXI, AHB)DDR/PCIe/Ethernet/ USB/ MIPIBe an individual contributor in the Verification Tasks – Architect testbenches, coding of TE, debug, verification coverage improvement, etc.Will contribute to technical review of TE Code of small and medium complexity.Will contribute to technical process and quality improvement to achieve high quality deliveries Will be expected to Solve complex/ abstract problems The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases in CRV environment.The candidate will work in a project and team oriented environment with teams spread across multiple sites, worldwide. May need to take the role of technical lead for a few of the components of the Test Environment and achieve high quality verification with a small team of verification engineers. The role offers ample scope to mentor junior engineers and interns and to enhance ones’ leadership skills.Bachelor's or Master's degree in EE with 3-4 years of relevant experience.Verification of IP Cores or SoC Designs for Set Top Boxes, Mobile handsets, Smart Devices, etc.Knowledge of one or more of protocols: AMBA (AMBA2, AXI, AHB)/ Ethernet/USB/ DDR/PCIe MIPIHands on experience with creating detailed design of components of Test Environment from Functional Specifications/ Test Environment Specifications. The TE must have used methodologies such as UVM/ VMM/OVM.Test Planning, Coverage Planning, Assertion PlanningHands on experience with System Verilog/SystemVerilog coding and Simulation tools; Knowledge of C++/ OOPs ConceptsExperience with Perforce or similar revision control environmentKnowledge of Perl/Shell scripts.Exposure to quality processes in the context of IP design and verification is an added advantageIn addition, the candidate should have good communication skills, will be a team player and will have good problem solving skills.