We are looking for a senior verification engineer to join us to develop the leading-edge interface digital IP.

Responsibilities:Understand customer requirements, understand protocols, and write test plans and verification schemes on this basis.Build testbench and testcase, execute the test according test plan and flow.Define function coverage and assertions, analyze the function coverage and code coverage, and make improvement to meet criteria.Lead or guide Junior engineers to complete the verification task.Key qualifications:Bachelor’s and/or master’s degree in electrical and/or Electronic Engineering, Computer Engineering or Computer Science.Minimum 6 years of IP and/or ASIC Verification experience is required.Knowledge in USB, Ethernet, PCI Express, UFS or DDR protocols.Good verbal and written communication skills in English.High degree of self-motivation and personal responsibility.Preferred Experience:Independently built UVM-based test benchASIC/SoC tape-out from concept to full production.Scripting languages (Shell, Perl, Python etc.)Silicon debug and FPGA/hardware troubleshooting skills