Job Responsibilities:
-- Working on architecture, RTL Design of SerDes targeted for high speed protocols.
-- Verilog RTL coding.
-- Spyglass (CDC, RDC), Lint. Lint, CDC, Synthesis flow, Formal checking, etc is a must.
-- Debugging issues/failures & working on customizations.
-- Hands on experience in SerDes design & high speed protocols like, PCIe, Ethernet..

Weightage:
-- Experience with Perforce or similar revision control environment
-- Knowledge of Perl/Shell scripts.
-- Verification skills & languages.
-- Good communication, Team player.
-- Interaction with customers.

Further opportunities:
-- FW development, FPGA prototyping/validation.

Educational background:
-- BE/B.Tech/M.Tech OR equivalent with minimum 4-5 years industry experience.