Job DescriptionsDefine and implement DFT architecture of IP designDo SCAN insertion and ATPG simulation (with and without timing)Analyze and improve test coverageSTA DFT timing constraints develop and analysisMake DFT integration guidelines to SoC levelComplete all design quality checks and data quality checksDo FMEDA, DFMEA analysis and report.Locate in Da NangSkills Requirements:BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications. 5+ years of experience in DFT designStrong knowledge of DFT architectures & methodologies which includes Scan insertion, ATPG, JTAG, etcHave knowledge in FUSA, ISO26262, FMEDA, DFMEA is a big plusStrong debug skills and demonstrated experiences in Perl /TCL/Python scripting is a plusStrong skill with design tools: Synopsys Design Compiler,  VCS, Formality, TetraMAXDesign experience in MBIST ,LBIST and Analog DFT is an added advantage.Highly responsible, result orientedGood English communication both verbally and in writingGreat team player, willing to support othersSelf-motivated and highly enthusiasm in technology and solving problems