We are looking for a senior design engineer to join us to develop the leading-edge interface digital IP.

Responsibilities:Understand customer requirements, understand protocols, and write mirco-architecture specification and RTL on this basis.Run Spyglass/VcSpyglass to check CDC/RDC/LINT and clean up issues.Write assertions and do formal verification.Run synthesis/STA/DFT. Analyze coverage data and provide solutions.Support Verification and FPGA validation. Key qualifications:Bachelor’s and/or master’s degree in electrical and/or Electronic Engineering, Computer Engineering or Computer Science.Minimum 4 years of IP and/or ASIC Design experience is required.Knowledge in USB, Ethernet, PCI Express, UFS or DDR protocols.Good verbal and written communication skills in English.High degree of self-motivation and personal responsibility.Preferred Experience:Independently work for IP/ASIC design.ASIC/SoC tape-out from concept to full production.Scripting languages (Shell, TCL, Perl, Python etc.)Silicon debug and FPGA/hardware troubleshooting skills