ASIC Digital Design, Staff Engineer
Synopsys (formerly Synfora)
The candidate will be part of the R&D in Solutions Group at our Bangalore Design Center, India. The position offers learning and growth opportunities. This is a Technical Individual Contributor role and offers challenges on technically challenging IP Cores in a role that will include IP design for the latest specifications.
Job Description
The candidate will be part of the Synopsys IP Design R&D team at Synopsys. He /She will be expected to specify, design/architect and implement state-of-the-art Synopsys family of synthesizable cores and perform Design tasks for the IP cores. He/ She will work closely with Verification team and be part of a global team of expert Design Engineers.
Will be working on the next generation connectivity protocols for Commercial, Enterprise and Automotive applications
Job role will have a combination of Architecture/Micro-Architecture development for the given specification, RTL coding, Implementation flows clean-up, debugging, document update and meeting quality metric goals.
Requirements:
Must have BSEE in EE with 5+ years of relevant experience or MSEE with 4+ years of relevant experience in the following areas:
- Must have experience in RTL coding, architecture and Mirco-architecture development or the given specification, CDC analysis, debugging waveforms, and meeting quality metric goals.
- Knowledge of one or more of protocols: MIPI-I3C/UFS/Unipro, AMBA (AMBA2, AXI), SD/eMMC, Ethernet, DDR, PCIe, USB
- Experience with MIPI UFS and Unipro protocols is a significant plus.
- Familiarity with HDLs such as Verilog and scripting languages such as Perl, TCL, Python is highly desired.
- Exposure to IP design and verification processes is an added advantage.
- There will be strong focus on quality RTL driven methodology. So, the corresponding mindset is a must.
- It is essential that the individual has good written and oral communication skills and can demonstrate good analysis, debug and problem solving skills and show high levels of initiative.
This position requires prior industry experience and is not open for college fresh grads.
Location: Bengaluru
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
Job Description
The candidate will be part of the Synopsys IP Design R&D team at Synopsys. He /She will be expected to specify, design/architect and implement state-of-the-art Synopsys family of synthesizable cores and perform Design tasks for the IP cores. He/ She will work closely with Verification team and be part of a global team of expert Design Engineers.
Will be working on the next generation connectivity protocols for Commercial, Enterprise and Automotive applications
Job role will have a combination of Architecture/Micro-Architecture development for the given specification, RTL coding, Implementation flows clean-up, debugging, document update and meeting quality metric goals.
Requirements:
Must have BSEE in EE with 5+ years of relevant experience or MSEE with 4+ years of relevant experience in the following areas:
- Must have experience in RTL coding, architecture and Mirco-architecture development or the given specification, CDC analysis, debugging waveforms, and meeting quality metric goals.
- Knowledge of one or more of protocols: MIPI-I3C/UFS/Unipro, AMBA (AMBA2, AXI), SD/eMMC, Ethernet, DDR, PCIe, USB
- Experience with MIPI UFS and Unipro protocols is a significant plus.
- Familiarity with HDLs such as Verilog and scripting languages such as Perl, TCL, Python is highly desired.
- Exposure to IP design and verification processes is an added advantage.
- There will be strong focus on quality RTL driven methodology. So, the corresponding mindset is a must.
- It is essential that the individual has good written and oral communication skills and can demonstrate good analysis, debug and problem solving skills and show high levels of initiative.
This position requires prior industry experience and is not open for college fresh grads.
Location: Bengaluru
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
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