We are seeking a Digital Verification Engineer who will be involved for functional verification of High Speed interface IPs.  A dynamic personality with eager to learn, drive Pre-silicon verification activities, good knowledge of digital design & HDL implementation.

Job DescriptionWork on Functional Verification of High speed serial link PHY IPs for USBx, PCIex, Ethernet, Display & HDMI protocol standardsIP/design blocks/Firmware Specification study and build/update verification plans as well as the test casesBuild/update functional verification environments to execute the test plansImplement checkers, assertions, random test generators, high level transactional models and bus functional models (BFMs) as per the verification plan needsPerforming simulation, random and direct stimulus development and coverage reviewWork closely with digital designers for debug and achieve the desired coverageRequirementsB.Tech/M.Tech with 5+ years of relevant experienceUnderstanding of functional verification flow with experience on industry standard development and verification tools and methodologies VMM, OVM/UVM and System VerilogExperience with System Verilog Assertions, code and functional coverage implementation and reviewScripting and automation using TCL/PERL/PythonExcellent debug and diagnostic skills