ASIC Digital Design, Staff Engineer
Synopsys (formerly Synfora)
The “R&D Professional” team has broad understanding in mixed-signal design, implementation, firmware and verification. The team has experience in both back-end and front-end ASIC development flows with a mandate to provide targeted support to mixed-signal High-Bandwidth Memory (HBM) and DDR PHY IP customers. We are looking for a candidate to join the team to help with front-end tasks. The ideal candidate will specialize in one of the following, experience in multiple areas would be a bonus:
ASIC RTL design and verification at chip level and/or block levelSolid Verilog, PERL, TCL and Python skillsUnderstanding of static timing analysis and synthesis, DFT/ATPG skills would be a plusKnowledge of any high-speed communication protocol is not mandatory but an assetPrevious knowledge in customer support and/or silicon bring-up is a plus
The diversity of tasks allow each team member to develop new skills and learn about all aspects of our PHY design. The main focus of the team is to support the application engineers solving customer problems, usually requiring deep investigations into the design. When not working on customer questions we use our knowledge to drive product improvements. Experience with HBM or DDR protocols is a definite asset but not mandatory. Your tasks will be adapted to your skills and development and will include some or all listed below:
Generate test benches and test casesPerform RTL and gate-level SDF-annotated simulations and debugMay perform mixed-signal (digital + analog) simulations and debugInteract with our application engineers and/or customers. Provide guidance to customers on HBM/DDR PHY front-end related (e.g. simulation, firmware, software, evaluation board) aspectsParticipate in the generation of data books, application notes, and white papersOther related duties as assigned by the manager
Key QualificationsBSEE degree or Applied Science degree (or equivalent) with 8+ years of related experienceExcellent communication and presentation skills
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
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Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.
ASIC RTL design and verification at chip level and/or block levelSolid Verilog, PERL, TCL and Python skillsUnderstanding of static timing analysis and synthesis, DFT/ATPG skills would be a plusKnowledge of any high-speed communication protocol is not mandatory but an assetPrevious knowledge in customer support and/or silicon bring-up is a plus
The diversity of tasks allow each team member to develop new skills and learn about all aspects of our PHY design. The main focus of the team is to support the application engineers solving customer problems, usually requiring deep investigations into the design. When not working on customer questions we use our knowledge to drive product improvements. Experience with HBM or DDR protocols is a definite asset but not mandatory. Your tasks will be adapted to your skills and development and will include some or all listed below:
Generate test benches and test casesPerform RTL and gate-level SDF-annotated simulations and debugMay perform mixed-signal (digital + analog) simulations and debugInteract with our application engineers and/or customers. Provide guidance to customers on HBM/DDR PHY front-end related (e.g. simulation, firmware, software, evaluation board) aspectsParticipate in the generation of data books, application notes, and white papersOther related duties as assigned by the manager
Key QualificationsBSEE degree or Applied Science degree (or equivalent) with 8+ years of related experienceExcellent communication and presentation skills
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Stay Connected: Join our Talent Community
Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.
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