Google welcomes people with disabilities. Minimum qualifications: + Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. + 3 years of experience with computer architecture concepts, including microarchitecture, cache hierarchy, pipelining, and memory subsystems. + Experience with Application-specific integrated circuit (ASIC) low power flows and power management concepts. Preferred qualifications: + Master's degree in Science or PhD in Electronics or Computer Engineering. + Experience with low power architectures/optimization techniques (e.g., clock gating, power gating, multi Vth, Dynamic Voltage and Frequency Scaling (DVFS)). + Experience with ASIC design flows from concept to post-silicon with Central Processing Unit, MultiMedia, Image Signal Processing. + Experience with ASIC power modeling/estimation, power goals, power management IP, peak power management, detection or mitigation, in-rush current, adaptive clock distribution or power/voltage domains design and power analysis. + Knowledge of software and architectural design decisions on system power and thermal behavior. Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. + Define and drive low power solutions for Google SoCs to optimize Power-Performance-Area (PPA) under peak current and thermal constraints. + Define power Key Performance Indicator (KPIs) and System on a chip (SoC)/IP-level power goals, guide architecture, design and implementation to achieve power goals, perform power roll ups and track power throughout the design cycle. + Propose and drive power optimizations throughout the design process from concept to mass production. + Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions. Model SoC and IP-level power and perform power rollups. + Perform post-silicon characterization and productization of power features. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCP_EEO_Post.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.