ASIC RTL/SoC Design Engineer Role Overview:
JSG is seeking a highly skilled ASIC RTL/SoC Design Engineer for our client to lead the design, simulation, and verification of ASIC/SoC products. The role will involve collaborating with multiple teams to optimize the performance and functionality of designs, integrating IP blocks, and supporting post-silicon testing and validation.
Key Responsibilities: Lead the RTL design, simulation, and verification efforts for ASIC/SoC products, ensuring efficient, high-performance designs. Integrate and validate IP blocks within the system, ensuring compatibility and smooth functionality. Analyze and optimize design trade-offs by performing Power, Performance, and Area (PPA) evaluations to meet both internal and external requirements. Collaborate with the backend team during RTL coding, implementation, and synthesis to ensure seamless tapeout and successful product delivery. Develop and maintain reusable internal intellectual properties (IPs), with a focus on AI and in-memory computing applications. Support Post-Silicon testing and validation, identifying and resolving issues to maintain product quality and functionality. Mentor and guide junior engineers, sharing knowledge and fostering their professional growth. Participate in design reviews and cross-functional discussions to provide feedback and enhance product performance. Stay informed on industry advancements and RTL design methodologies, incorporating innovative techniques to boost product quality and efficiency. Work closely with software, architecture, and verification teams to ensure a cohesive product development process. Qualifications & Skills: MS in Electrical Engineering (with 5+ years of experience) or PhD focusing on RTL/SoC/digital design. Proficient in Verilog and SystemVerilog. Experience with VCS, Verdi, or other industry-standard simulation and verification tools. Expertise in pre-layout and post-layout simulation. Strong understanding of the design flow and ability to work with the backend team. Familiarity with AMBA protocols (APB, AXI) and RISC/ARM or similar core architectures. Ability to create innovative architectural solutions to meet customer needs. Ability to thrive in a startup environment, both independently and within a team, providing technical leadership. Preferred Experience: Experience in FPGA/ASIC design for image processing systems. Knowledge of SoC architectures, including CPU, GPU, and accelerators. Familiarity with UVM, place-and-route, STA, and EM/IR/Power analysis.
Employment Type: Full-time
Pay Range: $110,000 - $300,000/year (DOE)
Location: Fremont, CA (On-site)

** Johnson Service Group (JSG) is an Equal Opportunity Employer. JSG provides equal employment opportunities to all applicants and employees without regard to race, color, religion, sex, age, sexual orientation, gender identity, national origin, disability, marital status, protected veteran status, or any other characteristic protected by law.