Application Deadline is expected to close 12/23/24.

Meet the Team

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. Come join us and take part in shaping Cisco's revolutionary solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

Your Impact

 As an ASIC Engineering Technical Leader, you will be responsible for leading the design, development, and optimization of application-specific integrated circuits (ASICs). You will ensure the integration of various design aspects, including timing closure, power optimization, area efficiency, and performance targets, while maintaining high standards of quality and reliability. You will act as a bridge between cross-functional teams, including physical design, verification, and software, to ensure alignment and resolve technical challenges. Responsibilities will include:

Leading architecture design and optimization in the early stages of chip development, focusing on timing context and budgeting for enhanced performance.Developing and refining timing and sign-off methodologies, driving the creation and implementation of SDC for various timing modes in the chip.Collaborating with physical and ASIC design teams to resolve timing and routing congestion issues, influencing key design and physical implementation decisions early in the process.Innovating and streamlining design flows, improving existing infrastructure to enhance timing sign-off efficiency and accelerate execution speed. 

Minimum Qualifications:

 • BS or MS Degree in Electrical or Computer Engineering with 10 Years Experience with ASIC design timing closure flow (STA) and methodology.

 • Hands-on experience with ASIC timing constraints generation and validation, clock domain crossing checks, and timing closure.

 • Expertise in STA tools (such as Primetime) and methodologies for timing, and simulating timing paths in Spice.

 • Demonstrated familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced process technology nodes (7nm and below).

• Experience in scripting languages (Tcl and Perl).

Preferred Qualifications:

 • Experience of Networking technologies and concepts.

 • Experience of asynchronous/CDC designs/implementations.

• Familiarity with RTL, synthesis, logic equivalence, DFT, and backend related methodology and tools.

• Strong communication and cross functional collaboration skills.

• Self-starter and highly motivated.

#WeAreCisco

#WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all.

Our passion is connection—we celebrate our employees’ diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best.

We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer—80 hours each year—allows us to give back to causes we are passionate about, and nearly 86% do!

Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. We ensure that every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us!