Proven experience (10+ years) in developing low-latency trading systems or high-frequency trading platforms using hardware acceleration techniques.Exceptional programming skills with a focus on performance optimization and hardware integration.Proficiency in low-latency Java libraries such as Chronical and other specialized Java collections like Eclipse, JCTools, etc., demonstrating a deep understanding of efficient data handling and processing in high-performance computing environments.In-depth knowledge of GC-free programming techniques, including object reuse, memory management, lock-free data structures, and minimizing memory allocations.Experience with low-latency messaging protocols and technologies, such as UDP, TCP/IP, or multicastKnowledge of algorithmic trading strategies, order types, market microstructure, and electronic trading platforms.Familiarity with hardware acceleration technologies, hardware description languages (e.g., Verilog, VHDL), and hardware-software co-design.Understanding of cache coherence protocols and cache optimization techniques for low-latency data access.Experience with CPU affinity, thread management, and multi-core optimization for high-performance computing.Optimize trading system performance by minimizing latency, optimizing code execution, and leveraging hardware acceleration.Collaborate with hardware engineers to design and integrate low-latency hardware solutions, such as accelerators and network cards.Conduct performance testing and analysis using hardware and software profiling tools such as JVisualVM, JProfiler, or YourKit to identify and address bottlenecks and inefficiencies.Monitor and maintain the stability and reliability of the trading platform, including troubleshooting and resolving technical issues related to hardware and software interactions.Integrate advanced cache coherence methodologies and fine-tune cache usage across L1, L2, and L3 caches to significantly boost data retrieval efficiency and drastically decrease latency within the system.Optimize the utilization of hardware resources by strategically managing CPU affinity and thread scheduling in multi-core environments.