Position: Bell Labs Platform & ASIC Research Co-op
Number of Position(s): 1
Duration: 4 Months 
Date: September 2 – December 19, 2025
Location: On-site (New Jersey, USA)

 

EDUCATIONAL RECOMMENDATIONS

Currently a candidate for a Ph.D. degree in Computer Science, Electrical Engineering, Computer Engineering, or Engineering in VLSI and telecommunication or a related field with an accredited school in the US.

*Highly qualified Master's students will be considered

At least TWO of below:

Advanced RTL development skills and fluent in HDL (SystemVerilog and VHDL) and/or HLS (High-level Synthesis) Experience in ASIC physical design tools: Cadence (Innovus, Spectre, Virtuoso) and Synopsys (VCS, ICC) Knowledge in micro-architecture, gate or RTL-level design optimization, timing closure analysis and/or mixed-signal circuit design AI/ML programming frameworks: TensorFlow, PyTorch, Keras, etc. Background in compiler, operating system, and kernel-level embedded software programming for parallel systems

As a part of our team, you will: 

Work with seasoned Bell Labs researchers on the design and development of ASIC and/or proof-of-concept platforms. Participate in a research project, work with a mentor(s) to define, develop, and conduct a research project, also can attend research talks in various technology areas. SoC research project will be in any of the following areas: Machine Learning Acceleration Digital signal processing and accelerator for 5G/6G communication systems Cloud-based radio access network Technologies for high-performance and scalable SoC design