As a Design Verification Engineer at Amazon, you will be part of an advanced engineering and research team that is building world class hardware for devices.

The ideal candidate should have experience with RTL development environments, fluency in modern hardware description languages and verification methodologies. They should have experience verifying complex IP blocks from scratch that have successfully been integrated in SOCs or other such silicon that have been productized in consumer devices. We are looking for a self-driven individual who can work with architects, HW and SW developers and can quickly resolve blocking issues.


Key job responsibilities
- Define the verification methodology and implement the corresponding test bench infrastructure in advanced HVL to verify world class hardware
- Communicate and work with team members across multiple disciplines
- Deliver detailed test plans for verification of complex digital design blocks by working with design engineers and architects
- Create and enhance constrained-random verification environments using SystemVerilog and UVM and write SVA.
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver functionally correct design blocks
- Close coverage measures to identify verification holes and to show progress towards tape-out
- Participate in test plan and coverage reviews

We are open to hiring candidates to work out of one of the following locations:

Sunnyvale, CA, USA