Arteris enables engineering and design teams at the world’s most transformative brands to connect and integrate today’s system-on-chips (SoCs) that fuel modern innovation. If you’ve held a smartphone, driven an electronic car, or powered up a smart TV, you’ve come in contact with what we do at Arteris. Here, the future is quite literally in your hands—and when it isn’t, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter! As a Design Verification Intern at Arteris your role will have Key Responsibilities: Test environment automation using scripting language ( TCL/Python/Java-Scripts)Testcases creation, checkers, assertions, coverage using System-Verilog and UVM methodologyRun test cases, debug failures for root cause .  Experience Requirements / Qualifications: Run test cases, debug failures for root cause .Debugging skills, fast learner and motivated to learn new things like UVM, Verilog, System-Verilog...etc.Excellent written and oral communication skills. Education Requirements: Enrolled in a related educational program

Estimated Base Salary:   $80 to $95 per hour About Arteris:Arteris is a leading provider of system IP for the acceleration of system-on-chip (SoC) development across today’s electronic systems. Arteris network-on-chip (NoC) interconnect IP and SoC integration automation technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so its customers can focus on dreaming up what comes next. With over 250 employees with headquarters in Silicon Valley and offices around the globe, we are a catalyst for SoC innovation so companies ranging from startups to the biggest technology market leaders can effectively create new products with proven connectivity flexibility and ease. Learn more at arteris.com.