MIT Lincoln Laboratory’s Advanced Technology Division develops advanced materials, devices, and subsystems that have broad impact on U.S. Government, industry, and academia. The Division has made a wide range of important contribu ons during the Laboratory’s 70+ year history, including development of bulk and epitaxial crystal growth, charge-coupled device (CCD) imagers, 193-nm lithography, fully depleted silicon-on-insulator (FDSOI) CMOS electronics, semiconductor diode lasers and amplifiers, superconduc ng electronics and quantum bit (qubit) devices, and photonic integrated circuits (PICs). To enable this advanced technology development, the Laboratory has implemented ver cally integrated in-house resources to facilitate design, lithographic mask layout, material growth and characteriza on, fabrica on (e.g., silicon, compound-semiconductor, wafer bonding, flip-chip hybrid), packaging, and tes ng of electronic and photonic circuits. These in-house resources are used to fabricate a variety of devices and circuits including lasers, waveguide photodetectors, op cal modulators, and CMOS and cryogenic electronics with applica ons in quantum compu ng, atomic systems, advanced laser sources, microwave photonics, communica ons, sensing, and other areas of interest to the U.S. Government, industry, and academia. In-house fabrica on resources include: •Microelectronics Laboratory (ML): Cleanroom housing a silicon-fabricati on toolset operati ng on 200-mm-diameterwafers at a 90-nm lithography node, which represents the most advanced silicon fab in the U.S. Government labsystem. •Compound Semiconductor Laboratory (CSL): Faciliti es housing III-V and non-silicon material growth (molecular beamepitaxy (MBE), metalorganic chemical vapor depositi on (MOCVD), diamond chemical vapor depositi on (CVD)) andfabricati on •Microsystems Integrati on Facility (MIF): Packaging and integrati on faciliti es for wire-bonding, vacuum-refl owsoldering, fl ip-chip hybrid integration Job Description The candidate will work as a member of a multi-disciplinary team responsible for implementing, applying, maintaining, maturing, and using process design kits (PDKs) for silicon-based, compound-semiconductor, and heterogeneous/hybrid fabrication processes, especially those for photonic integrated circuits (PICs). The candidate may also work on PDKs for superconducting qubit and trapped-ion qubit quantum computing, radiation-hard CMOS, and other emerging integrated circuit technologies. Further, the candidate will help with, and may lead, mask layouts using these PDKs. The engineer will work in the Cadence environment, with which they should be fluent. Key development tasks include the creation of technology files, coding parameterized cell libraries, documenting code and methodology updates, and documenting layout changes. Key layout tasks include reticle floor planning, and device, test structure, circuit, and full mask layout. The engineer will collaborate with others involved in mask layout from basic layout cell creation and floor-planning to final tapeout. Creation of DRC and LVS decks as these technologies mature will likely be required. Note that many of these technology areas are cutting edge and processes and PDKs will be continuously and rapidly evolving. Required Qualifications •Masters degree required •Five or more years’ experience with developing technology files and design environments in Cadence or similartools •Five or more years’ experience with coding parameterized layout cells, ideally in the Cadence Virtuoso (SKILL)environment•Experience working on multiple inter-related PDKs and layouts •Ability to work independently with minimal supervision and collaboratively as part of a dynamic, multi-disciplinaryteam •Excellent organization and communication skills both within and across disciplinary boundaries Preferred Qualifications: •Experience with photonic integrated circuit PDK development or mask layout a major plus •Experience with mask floor-planning, creating custom layout blocks, and mask aggregation •Experience with LVS beyond traditional CMOS technologies •Experience with or knowledge of one or more of the following areas: oThe Advanced-Node version of Cadence oProgramming in Perl, TCL, or Python oRF layout design experience oExperience with Cadence CurvyCore At MIT Lincoln Laboratory, our exceptional career opportunities include many outstanding benefits to help you stay healthy, feel supported, and enjoy a fulfilling work-life balance. Benefits offered to employees include: + Comprehensive health, dental, and vision plans + MIT-funded pension + Matching 401K + Paid leave (including vacation, sick, parental, military, etc.) + Tuition reimbursement and continuing education programs + Mentorship programs + A range of work-life balance options + ... and much more! Please visit our Benefits page (https://hr.mit.edu/benefits) for more information. As an employee of MIT, you can also take advantage of other voluntary benefits, discounts and perks (https://hr.mit.edu/benefits/additional) . Selected candidate will be subject to a pre-employment background investigation and must be able to obtain and maintain a Secret level DoD security clearance. MIT Lincoln Laboratory is an Equal Employment Opportunity (EEO) employer. All qualified applicants will receive consideration for employment and will not be discriminated against on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, age, veteran status, disability status, or genetic information; U.S. citizenship is required. Requisition ID: [[id]] #LI-CA1