Roseville, USA
10 days ago
Engineer I - Design

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Job Description:

The Architecture Co-Verification team (ACOV) is an exciting, fast paced team responsible for enabling HW/FW development and co-verification of state-of-art System-On-Chip (SoC) devices using industry leading HW emulators (such as Cadence Palladium and Protium).  The team is deployed in all aspects of SoC development phases from architectural exploration to post-silicon validation, HW/FW co-development, pre-silicon functional co-verification, pre/post-silicon performance testing, power analysis, and critical post-silicon investigations.

As a Design Engineer, you will be working closely with hardware designers, firmware engineers, and verification teams throughout the SoC development process. 

This is a role for a versatile engineer that enjoys the challenges of HW/FW co-development and system level co-verification using leading edge HW emulators and FPGA platforms.  It’s a high visibility role that will develop a wide range of skills and exceptional problem-solving ability.

Responsibilities could include but are not limited to the following:

Porting SoC RTL to industry leading HW emulators and FPGA platforms.Developing emulation specific HW for pre-silicon subsystem/system level co-verification.Developing common test ecosystem across pre/post siliconDeveloping FW/tests for pre-silicon subsystem/system level co-verification.Troubleshoot and resolve complex problems in embedded multi-core real-time systems executing co-verification test plans.Utilize state of the art logic analysis and protocol analyzersUtilization of test and defect tracking tools to document and report on verification progress and product qualityEffectively present technical information to small teams of engineers.

Requirements/Qualifications:

BS/MS degree in Electrical/Electronic Engineering or Computer EngineeringExcellent analytical and documentation skillsStrong problem solving, communication and interpersonal skills are requiredExperience with Verilog and/or VHDL is an assetExperience with the ASIC design and/or verification flow is an assetWilling to learn in a fast-paced environment, being a self-starter, and organizedStrong programming and scripting skills with languages such as C, Python, Tcl, Bash, C shellHighly motivated team player who sets personal goals and achieves those goals with minimal supervision


Desired Skills:

Experience with storage protocols and interfaces is an asset (PCIe, NVME, CXL, SAS)Experience working in Linux and Windows Environments and file system structures.Familiarity in system level emulation techniquesFamiliarity with hardware design and implementation.Knowledge of MIPS and/or ARM CPU architecture and firmware programming

Travel Time:

0% - 25%

Physical Attributes:

Carrying, Feeling, Handling, Hearing, Seeing, Talking, Works Alone, Works Around Others

Physical Requirements:

Regular business hours. 70$ sitting, 15% standing, 15% walking

Pay Range:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below:

Benefits of working at Microchip

The annual base salary range for this position, which could be performed in California, is $66,560 -$128,000.*

*Range is dependent on numerous factors including job location, skills and experience.

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.

For more information on applicable equal employment regulations, please refer to the EEO is the Law Poster and the EEO is the Law Poster Supplement. Please also refer to the Pay Transparency Policy Statement.

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