Job Description
We are seeking a skilled Digital ASIC/FPGA Design Engineer to support our Satellite Capabilities organization and multiple satellite product lines based in El Segundo, CA. The ideal candidate will utilize high-level architectural documentation along with algorithm descriptions to implement DSP functions and develop mathematical models in System Verilog to verify design implementation.
ResponsibilitiesUtilize high-level architectural documentation along with algorithm descriptions to implement DSP functions such as decimation, interpolation, general filtering, up-down conversion, digital beam forming, and channelization.Develop mathematical models in System Verilog to verify design implementation.Develop and run scripts and make files.Architect block level design specifications based on system requirements.Prepare detailed design documentation.Perform HDL coding, logical equivalency checking, static timing analysis, CDC, and linting.Integrate third-party IP.Create self-checking and reusable test benches from scratch, utilizing Object Oriented Programming concepts.Develop Functional Coverage Models and close Code Coverage.Essential Skills3 or more years of experience in digital ASIC/FPGA design and verification.Proficiency in Verilog or System Verilog.Bachelor, Master, or Doctorate of Science degree from an accredited course of study in engineering, computer science, mathematics, physics, or chemistry.Experience with HDL coding, logical equivalency checking, static timing analysis, CDC, and linting.Experience developing mathematical models in System Verilog.Additional Skills & QualificationsBachelor's degree with 7 or more years of experience in digital ASIC/FPGA design and verification, Master's degree with 5 or more years of experience, or PhD degree with 2 or more years of experience.5+ years of experience with Universal Verification Methodology (UVM) sequences and virtual sequences.5+ years of experience using Linux or Unix terminal commands.Experience with scripting languages such as Make, Perl, Python, and shell scripts.Experience with Revision Control Systems like Subversion (SVN), CVS, and Git.Experience writing requirements specification documents.Experience writing architectural design documents with detailed design blocks and timing diagrams.Experience performing RTL synthesis.Experience performing Static Timing Analysis and correcting timing violations.Experience simulating digital designs using hardware verification languages such as System Verilog and System Verilog Assertions.Experience using Object Oriented Programming concepts.Work Environment
This position is based in El Segundo, CA. It involves working with advanced technologies and equipment in a dynamic and collaborative environment.
Pay and BenefitsThe pay range for this position is $100000.00 - $175000.00
PTO, Vacation, Full medical, 401k, Holiday pay, PTO, Vacation, Full medical, 401k, Holiday pay, PTO, Vacation, Full medical, 401k, Holiday pay
Workplace Type
This is a fully onsite position in El Segundo,CA.
Application Deadline
This position will be accepting applications until Dec 31, 2024.
About Actalent
Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 30,000 consultants and more than 4,500 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500.
Diversity, Equity & InclusionAt Actalent, diversity and inclusion are a bridge towards the equity and success of our people. DE&I are embedded into our culture through:
Hiring diverse talent Maintaining an inclusive environment through persistent self-reflection Building a culture of care, engagement, and recognition with clear outcomes Ensuring growth opportunities for our peopleThe company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.
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