SummaryPosted: Dec 16, 2024Weekly Hours: 40 Role Number:200583210Imagine what you could do here. At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish! Dynamic, resourceful people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. Join the team that optimizes and delivers world-class GPUs into Apple Silicon. As part of the GPU FE Implementation team, you’ll be responsible for crafting and building a GPU that enriches the lives of millions of people every day.DescriptionDescriptionCandidates will be responsible for RTL to netlist generation working collaboratively with the RTL and Physical design teams. You will also deliver key netlist quality milestones for your partition, engage in Lint, CDC, Logic equivalence checks and support ECO generation activities. Through this collaboration, you will deliver the best-in-class GPU’s for the best consumer products. If you’re ready to help chart the future of Apple Silicon, we’d love to talk to you.Minimum QualificationsMinimum QualificationsExperience with at least one of the following scripting languages: python, perl, tclBS requiredKey QualificationsKey QualificationsPreferred QualificationsPreferred QualificationsRelevant Coursework in Computer Architecture, Digital Logic Design and CMOS VLSI designFamiliarity with Verilog and System VerilogExposure to industry standard rtl2gds tools for synthesis, place and route, static timing analysisExposure to Clock/Reset domain crossing or Voltage crossing principlesFamiliarity with DFT methodologiesKnowledge of static timing analysis concepts (setup and hold timing)Understanding of CMOS device characteristics for area/timing/power tradeoffsEducation & ExperienceEducation & ExperienceAdditional RequirementsAdditional RequirementsMore

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