Overview:

We are looking for an experienced Mask Layout Design Engineer who is innovative and has a passion for IC Layout design of high-speed CMOS Interface D2D and SERDES for next generation Consumer Cloud Computing Devices.

The ideal candidate is a self-starter highly motivated engineer with excellent technical interpersonal skills used to working independently or as a key member of a fast-moving design team.

Responsibilities:

The primary responsibility of this position entails executing IC layout of cutting edge high-performance high-speed low power CMOS Interface D2D and SERDES integrated circuits in foundry CMOS process nodes in 2nm and 3nm following industry best practices.

You will be responsible for all or parts of the following areas:

- Using Cadence Virtuoso design tool and flow

- Will be working on highly analog IPs like analog PLL DLL ADC RX TX OTAs LDO Clock Distribution Bandgap and Bias

- Layout Design review presentations.

- Layout floor-planning and supervision.

- Physical LVS DRC DFM

Candidate Requirements

- Years of Experience Required: 0-2 overall years of experience in the field.

- Degrees or certifications required: NO degree is required to be eligible for this role.

- MSFT experience is nice but not required.

Qualifications:

- You should have min 1 years of experience in high performance analog layout in advanced FINFET CMOS process 2nm and 3nm preferred BS degree a plus

- Detailed knowledge of EDA tools for Cadence Mentor and Synopsys.

- Having experience with layout of high-performance analog blocks such as VCOs chargepump phase interpolators clock distribution bandgap OTAs PLLs ADCs LDOs RX TX references etc. is desired.

- Knowledge of analog design and layout guidelines and high-speed IO.

- Experience with floor planning block level routing and large macro level assembly.

- Knowledge of high-performance analog layout techniques such as common centroid layout matching symmetrical layout signal shielding use of dummy devices thermal aware layout with consideration for electro migration IR ESD and other analog specific guidelines.

- Confirmed experience with analog layout for silicon chips in mass production.

- Worked with sub-micron design in foundry CMOS nodes 2nm 3nm and 5nm FINFET.

- Requires self-starter with the ability to define and adhere to a schedule

About Actalent

Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 30,000 consultants and more than 4,500 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500.

Diversity, Equity & Inclusion

At Actalent, diversity and inclusion are a bridge towards the equity and success of our people. DE&I are embedded into our culture through:

Hiring diverse talent Maintaining an inclusive environment through persistent self-reflection Building a culture of care, engagement, and recognition with clear outcomes Ensuring growth opportunities for our people

The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.

If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing process due to a disability, please email actalentaccommodation@actalentservices.com for other accommodation options.