Description

Typical Day in the Role

- Purpose of the Team: The purpose of this team is create custom silicon for client.

- Key projects: This role will contribute to with some IPs going into some chips for client's products- generating fabric stitching together connecting modules.

- Typical task breakdown and operating rhythm: The role will consist of 20 meetings and 80 coding.

Compelling Story Candidate Value Proposition

- What makes this role interesting? - This role provides the opportunity to work on cutting edge technology for next generation of products_.

Candidate Requirements

- Years of Experience Required: 8 years of experience in hardware design

- Degrees or certifications required: Bachelors degree in Electrical Engineering Computer Engineering or related degree required to be eligible for this role.

- Disqualifiers: Candidates with constant job hopping need to be able to stick out the contract lack of recent experience of the sub system integration or building fabrics will not be eligible for the role.

- Best vs. Average: The ideal resume would contain strong knowledge in fabric and ARM architecture..

- Performance Indicators: Performance will be assessed based on meeting deadlines.

Top 3 Hard Skills Required Years of Experience

1. Minimum 3 years of Strong design knowledge of the industry standard bus interfaces such as AMBA AXI protocol.

2. Minimum 3 years with Knowledge of the ARM architecture.

3. Minimum 7 years expertise in Digital Design including microarchitecture specification development RTL coding in Verilog/System Verilog and Clock Domain Crossing CDC/LINT closure.

Hard Skills Assessments

- Expected Dates that Hard Skills Assessments will be scheduled: after 8/29.

- Hard Skills Assessment Process: The assessment process will include 1 round of assessments.

- Required Candidate Preparation: Candidates should have experience talking on past experience prepared prior to the assessment.

Job Description

Summary:

Front-End Silicon Design Engineer who is responsible for front end design tasks at the block and sub-system levels. These tasks include RTL design sub-system integration RTL generation via 3rd party tools and repository management.

Job Responsibilities:

- Responsible for various integration tasks at the block level

- Responsible for various integration tasks at the sub-system level

- Responsible for generation of cores Cadence Tensilica

- Responsible for the generation and integration of NOCs Synopsys and Arteris

- Manage repos for shared collateral across design teams

Skills:

- Knowledge of the ARM architecture

- Knowledge of Cadence Tensilica cores

- Strong design knowledge of the industry standard bus interfaces such as AMBA AXI protocol

- Worked with leading-edge technologies 5 nm or smaller.

- Knowlege of GIT repositories

Education/Experience:

- Bachelors degree in Electrical Engineering Computer Engineering or related degree required.

- 8 years of experience in hardware design

- 7 years expertise in Digital Design including microarchitecture specification development RTL coding in Verilog/System Verilog and Clock Domain Crossing CDC/LINT closure.

Experience Level

Intermediate Level

We reserve the right to pay above or below the posted wage based on factors unrelated to sex, race, or any other protected classification.

Eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. This temporary role may be eligible for the following:

Medical, Dental & Vision401(k)/RothBasic/Supplemental Life & AD&DShort and long-term disabilityHSA & DCFSATransportation benefitsEmployee Assistance ProgramCompany Paid Time off or State Sick Leave

Pay and Benefits

The pay range for this position is $56.00 - $62.00/hr.

Eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. If eligible, the benefits available for this temporary role may include the following:

• Medical, dental & vision
• Critical Illness, Accident, and Hospital
• 401(k) Retirement Plan – Pre-tax and Roth post-tax contributions available
• Life Insurance (Voluntary Life & AD&D for the employee and dependents)
• Short and long-term disability
• Health Spending Account (HSA)
• Transportation benefits
• Employee Assistance Program
• Time Off/Leave (PTO, Vacation or Sick Leave)

Workplace Type

This is a fully remote position.

Application Deadline

This position is anticipated to close on Jan 31, 2025.

About Actalent

Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 30,000 consultants and more than 4,500 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500.

Diversity, Equity & Inclusion

At Actalent, diversity and inclusion are a bridge towards the equity and success of our people. DE&I are embedded into our culture through:

Hiring diverse talent Maintaining an inclusive environment through persistent self-reflection Building a culture of care, engagement, and recognition with clear outcomes Ensuring growth opportunities for our people

The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.

If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing process due to a disability, please email actalentaccommodation@actalentservices.com for other accommodation options.