We’re looking for an experienced signal integrity engineer to join the team.
Does this sound like a good role for you?
In this position, you will be part of a team that designs the next-generation DDR and HBM PHYs in the Synopsys IP portfolio.  The position entails evaluating the electrical performance of memory interconnect channels, evaluating strategies for improved signaling at ever-increasing data rates, generating reports, and communicating results, trends, and recommendations to internal design teams and to customers.  You will leverage your understanding of off-chip signaling, interconnect construction, channel modeling, signal and power delivery analysis, and electromagnetic behaviors to drive Synopsys’ evolving portfolio of leading-edge products.  You will join a collaborative, multi-person engineering team covering an array of DDR, HBM, UCIe PHY development projects.


Job Responsibilities:Perform interconnect assessments using the latest modeling techniques to predict channel data rates and signal marginsAssess strategies for system performance optimization, including signal margins, power, and FFE, DFE, and CTLE equalization techniquesAssess power delivery systems to optimize power integrity for supply stability and jitter minimizationDocument findings in reports and design guidelinesCommunicate results and insights to design teams to improve PHY designCommunicate results and recommendations to customers to enable them to optimize their system performanceInteract with design teams and customers to refine and apply signal and power analysis methods to refine strategies and address problemsUnderstand Synopsys’ DDR and HBM PHY roadmap and create strategies for improved performance Track industry developments through activities at standards committees and through memory vendor roadmaps
Key Qualifications and Experience:Proven understanding of high-speed interface signaling operation, such as s-parameters, channel loss, crosstalk, equalization techniques, jitter, and power delivery modelingWell-versed in signal and power delivery analysis methods, including eye diagram construction through statistical modeling, return loss, impedance matching, and resonant system analysisSkilled in generating and communicating results, findings, conclusions, and recommendations within a design team and to external customersWell-versed in signal and power integrity analysis tools, HSPICE, IBIS, IBIS-AMIKnowledgeable in board-level construction and on-chip IO design operationAble to work across a multi-site team to communicate ideas, understand problems, and find solutions to create a leading-edge designPossessing a minimum of 3 years of related experienceThe base salary range across the U.S. for this role is between $125,000-$187,000 annually. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.