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Job Description:

BSEE and 6 years’ experience required, MSEE/Ph. D. preferred.Demonstrated Analog IC design experience using SOI CMOS, bulk CMOS, and SiGeDeep understanding of associated analog control and bias circuitsDeep understanding of Analog device modeling, including device noise parameters and operation function modeling. Insights into packaging effects, supply isolations, high frequency ESD structures, and circuit layout for optimum Analog front-end performance.Deep understanding of analog operational amplifier for high speed, low power consumption, stable performance. Deep understanding of power LDO & charge-pump & programmable gain D/A for high speed, low power consumption, stable performance. Proficient with Cadence Spectre, BDA and ADS simulation tools (S-parameter, HB, envelope)Layout experience using the Cadence flow, including LVS and DRC. Ability to work with CAD engineers and provide guidance on RF and analog layoutsVaried type of Analog front-end system experience is strong plus, especially from system concept to IC design.Working on the Korean site is required. Must be able to communicate fluently in English and Korean.

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