Company:Qualcomm Semiconductor Limited

Job Area:Engineering Group, Engineering Group > ASICS Engineering

General Summary:

This is a Verilog modeling and characterization engineer position in Methodology, Flow and Design Kit team involved in defining methodologies, flows and in delivering design kit including behavioral models and timing models for I/Os, memories and standard cell libraries in state of art CMOS/FinFET technology nodes for Qualcomm's advanced mobile baseband, Auto, IOE/IOT & consumer products.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.

Job Responsibilities

Write RTL models in Verilog for the different flavors of IOs.Build verification plan and verify the design including both behavioral models and transistor level implementation.Experience in System Verilog assertions(SVA), Power aware verification and formal verification is necessary.Debug issues at IP level and SoC level.Prior experience in analog/mixed signal simulations is preferred.Solid understanding of VLSI circuits and Spice simulator experience along with commercial characterization tool experience is expected.Understand the I/O circuit architecture and write stimulus for Timing/Power characterization.Need to be familiar with various Liberty models including NLDM, CCS, LVF.Work with internal customers to understand the requirements and support the SoC team on behavioral models and timing models throughout the design cycle.Exposure to RTL to GDSII flow is required. Understanding of STA and exposure to the flow is necessary.Interaction with tool vendors to drive the flow improvements and methodologies to address the requirements from latest technologiesSolid understanding of VLSI circuits and Spice simulator experience along with commercial characterization tool experience is expected.Drive and build automation with any of the scripting languages like Python/Perl/TCL to improve the productivity and quality.Responsible for developing new methodologies and flows to support complex designs, driving the design verification reviews, automation and drive productivity & quality.

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Minimum Qualifications

Bachelor's degree in Science, Engineering, or related field.
 

Preferred Qualifications

Bachelor's degree in Electrical Engineering, Computer Science, or Computer Engineering.3+ years in RTL coding, Verilog and System Verilog Test benches, Design verification, IP characterization or related work experience.2+ years experience with design verification methods.2+ years experience with scripting tools and programming languages.

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