Our team is looking for an experienced Memory Layout Design Engineer who plays a critical role in layout design for various foundation IPs, especially TCAM IP. 

Responsibilities:
In the role of a Senior Layout design engineer, you will take the responsibility to:

Design, develop and modify layout design for Embedded Memory IPs, Standard Cells, IOs

Improve and Determine methods and procedures for Layout development flow

Key Qualifications

Bachelor’s or Master’s degree, Electronics Engineering, Telecommunication, Physics or related fields

Typically, a minimum of 2 years of experience in Layout design

Advanced knowledge of Custom Layout and a deep understanding of Embedded Memory Layout.

Strong communication, documentation and analytical skills.

Get to know more about Synopsys Foundation IP: Logic Library, Memory Compiler, OTP, NVM | Foundation IP | Synopsys

Synopsys delivers leading silicon to systems design solutions that maximize our customers’ R&D capability and productivity. Companies trust Synopsys to pioneer new technologies getting them to market faster without compromise.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.