Job TitleMaster Thesis - Optimizing Coverage Closure for ASIC Verification: A Reference Model-Driven Approach to Stimuli Generation

Job DescriptionCategory

Computer Science, Electrical Engineering

Scope

Two students completing 30 credits (20 weeks) each

Introduction

In hardware verification, ensuring a design meets all functional requirements is a complex, time-consuming process known as coverage closure. This thesis proposes an innovative two-phase approach using a golden reference model to streamline stimuli generation and coverage analysis before final design simulation, significantly accelerating verification. By comparing this method with conventional approaches, the study aims to highlight the advantages of a faster, more efficient coverage closure process in hardware development.

Background

The hardware development flow begins with a digital representation of the hardware design, typically using a hardware description language (HDL), such as VHDL or SystemVerilog. This description defines the circuit's structure and functional behaviour. A golden reference model, which is generally a higher-level, software-executable model of the hardware, serves as the specification for the hardware.

To verify the functional correctness of the hardware design, it is simulated in a software-based execution environment. Specific programs generate random input vectors (stimuli) and apply them to both the design and the golden reference model. During simulation, the design's response is monitored and compared to the result of the golden reference model. This self-checking process ensures correctness for the simulated scenarios.

“Coverage closure” is a term used to describe the process of ensuring that a set of predefined coverage goals are met through simulations. The collected coverage data from simulations is analysed to determine which parts of the design have been exercised and which aspects still need to be verified. It provides insight into the completeness of the verification process and identifies areas where coverage goals have not been met.

Coverage closure involves modifying the test scenarios to include additional test cases or corner cases that help improve coverage. After making the necessary adjustments, the simulation is re-run, and the coverage analysis is performed again. This process is iterative and may require multiple cycles of simulation, analysis, and refinement until the coverage goals are met.

SystemVerilog simulations are discrete event-driven and operate at a low level of abstraction. These simulations deal with individual clock cycles, signal transitions, and specific timing requirements of hardware. This level of granularity demands more processing power and time, and compared to the randomization of stimuli, they tend to be the performance bottleneck in the coverage closure process. Individual simulation runs commonly last for hours and, in some cases, even days.

A proposal to limit this bottleneck is to perform the coverage closure in two separate phases. The first phase disables the simulation of the design but executes the golden reference model for coverage collection and closure. This is followed by a second phase of correctness checking, where the design is reintroduced and subjected to simulations with the tests produced in the first phase. Given that the golden reference model executes in zero simulation time, the first phase could potentially be a fast iterative process, enabling a faster overall coverage closure.

Additionally, this technique can enable 'shift-left' verification. This means that even if the HDL representation of the design is unavailable, progress can still be made if the reference model is available.

Goals

The goal of this project is to evaluate, propose and implement a concrete coverage closure flow, including

Comparative analysis of traditional coverage closure flow vs. reference model targeted. At the end of the project there should be a clear understanding of the benefits and caveats of using such a flow in the coverage closure process.

Who are you?

This thesis proposal is suitable for students with an interest in both hardware and software development - you are most likely part of a Computer Science or Electrical Engineering program. Experience in Python programming is preferred.

OK, I am interested! What do I do now?

You are valuable to us – how nice that you are interested in one of our proposals! There are a few things for you to keep in mind when applying.

Applications are accepted in both Swedish and English, and you apply via the proposal advert.The announced thesis is open only to students affiliated with a Swedish University/College either directly or via an exchange program.It is mandatory to apply in pairs. Send one application for each pair but make sure to clearly state in your application who your co-applicant is. If you have any questions regarding this, please do not hesitate to contact us.It is also required to attach the CV and University/College grade transcript from both students.

Who to contact for any questions

For more information, contact Per Dagermo Engineering Manager at the ASIC Verification department, per.dagermo@axis.com.

Type of EmploymentTemporary Employment (Fixed Term)

Posting End Date2025-01-09

Certain roles at Axis require background checks, which means applicable verifications will be done in these recruitments. Notice will be provided before we take any action.

About Axis Communications

We enable a smarter, safer world by creating innovative solutions for improving security and business performance. As a network technology company and industry leader, we offer solutions in video surveillance, access control, intercom, and audio systems, enhanced by intelligent analytics applications.

With around 4500 committed employees in over 50 countries, we collaborate with partners worldwide. Together, we thrive in our friendly, open, and collaborative culture and inspire each other to think beyond the expected. United by our commitment to inclusion, diversity, and sustainability, we consistently seek to develop our skills and way of working.

Let´s create a smarter, safer world

For more information about Axis, please visit our website www.axis.com.

Listen to Get To Know Axis – Podcast