Company:Qualcomm Technologies, Inc.Job Area:Engineering Group, Engineering Group > ASICS Engineering
General Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.
The infrastructure IP Team consists of a multi-disciplinary group involved in the definition and design of Platform infrastructure HW components such as Memory controllers, System cache, System MMU and Interconnect that are implemented in all Qualcomm SoCs. This position primarily involves studying System Performance using cycle-accurate/approximate models and support both Infra IP level u-architecture optimizations as well as System level application performance verification. The ideal candidate should demonstrate the ability to understand the HW u-architecture of the infrastructure components involved, the memory system and interconnect, identify performance bottlenecks; define experiments and conduct data-driven performance analyses and debug using simulation; Ability to partner effectively with IP designers, Design Verification teams and System performance architects.
Principal Duties and Responsibilities:
Work with experts in other domains, such as CPU, GPU, Display, Camera, and others, to understand their cache usage requirements, and help drive architecture and design decisions.Modeling and analysis of system cache, replacement algorithms, and featuresDevelop tests, test plans and testing infrastructure for new architecture/featuresConduct in-depth analysis of product requirement dashboards, CPU/GPU/MISC benchmarks to identify memory bottlenecks and areas for improvement.Demonstrates good understanding of and conducts research on industry trends and innovations in memory subsystem to ensure solutions and deliverables align with best practices.Drive model development best practices, coding guidelines and process automationsPreferred Qualifications
Self-driven, methodical and process oriented.Excellent oral and written communicationSound understanding of System interconnect, Caches and Memory Technologies (e.g. LPDDR4/5)Experience with SoC Performance analysis and debug in pre and/or post-silicon environmentsGood understanding of QoS conceptsGood handle in Object oriented programming and general SW debug (C++)Strong scripting skills (Perl/Python)Experience with data analysis using Excel, R, Python etc.
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
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Pay range and Other Compensation & Benefits:
$134,500.00 - $215,000.00The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.