At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Performance Modeling Engineer

Location – US (prefer – San Jose)

Summary

Chiplet-based system design is an emerging trend in semiconductor technology, offering a new paradigm for building complex systems-on-chip (SoCs). Cadence is at the forefront of this innovation, unveiling the first system chiplet.

As part of the System Architecture team you will focus on performance by developing and integrating event-driven, cycle-level performance models for various Cadence IPs (including NoC, NPU, Memory Controller, UCIe), building chiplets and chiplet based systems, creating methodologies for architectural exploration, identifying key performance indicators to drive cutting-edge solutions for chiplet based SoCs.

Responsibilities

Develop a model-based performance analysis framework facilitating fast and accurate simulation at the chiplet and system levelPerform architectural exploration and quantify system performance for different workloads (traffic generators, CPUs, GPUs) and benchmarks - datacenters, AI inference, automotive, applicationsCollaborate with system and IP architects to translate findings into practical solutions that can influence the design and application of chiplet technologyDefine system performance specification and work with RTL performance verification teams in correlating expectations

Required Skills/Experience

At least 5 years of experience in performance modeling and analysisUnderstanding of performance concepts, queuing theory, throughput/latency tradeoffsStrong programming concepts: C++, SystemC/Transaction Level Modeling (TLM)In depth understanding of computer architecture and memory hierarchyBachelors/Masters/PhD in Computer Science, Electrical Engineering or similar

Preferred Skills

Knowledge of memory controllers and memory protocols – DDR, LPDDR, HBM, etcPrior experience developing models for components such as CPU, NoC, GPU, MMU, Caches, memory controllersUnderstand of interconnect protocols like AHB/AXI/ACE/ACE-Lite/CHIExperience working with a full system simulator like GEM5, or similarExperience working with performance benchmarks – SPEC, STREAM, accelerator workloads, generating synthetic traffic representing real traffic

Understand RTL-Verilog, SV, UVM and experience with performance verificatio

The annual salary range for California is $150,500 to $279,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.