SummaryPosted: Jan 31, 2025Role Number:200589278Imagine what you could do here at Apple? Together we could help craft the next generation of the world’s finest devices. New ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your career, and there's no telling what you could accomplish! We searching for a self-motivated engineer for the role of ASIC timing engineer. You will engage with forefront technology nodes to build outstanding custom silicon designs used to connect our extraordinary products to the world as well as optimizing their performance. You will join a development team that values engineering excellence, creativity and innovation. You will become a valuable member of Apple's Japan Design Centre! Dynamic, smart people and inspiring, innovative technologies are the norm here. Will you help us design next revolutionary Apple products?DescriptionDescription- Work with design teams to understand and debug constraints and facilitate logic changes to improve timing. - Work with the Physical Design team, highlighting issues and best practices. - Help create timing ECO’s for project tapeout. - Create and maintain scripts and methodologies for analysis and runs. - Create documentation and help with guidelines/specs. - Deep analysis of timing paths to identify key issues. - Implement timing infrastructure. - Work on place & route, CTS, timing convergenceMinimum QualificationsMinimum QualificationsWe are looking for experienced applicants with strong understanding of the RTL2GDSII flow and concepts related to synthesis, place & route, CTS, timing convergence.Typically requires more than 5 years of hands on experience in STA/P&R.Familiar with important aspects of timing of large high-performance/low-power SoC designs.Proficient in STA and methodologies for timing closure and have a fundamental understanding of noise, crosstalk, and OCV effects, among others.Experienced in industry standard tools used for STA such as Synopsys PrimeTime, Cadence Tempus, etc.Scripting skills with TCL, Python and Perl to debug flow related issues and make enhancements as appropriate.Familiar with worst-case corner selection.Experience with STA on large, complex designs and Multi-Scenario Timing Closure.Knowledgeable in partition level P&R implementation, including floorplanning, clock and power distribution, timing closure, physical and electrical verification is a plus.Familiar with ECO techniques and implementation.Good communicator who can accurately describe issues and follow them through to completion.English verbal communication is required.Bachelors of Science, preferred in Electrical EngineeringKey QualificationsKey QualificationsPreferred QualificationsPreferred QualificationsFamiliar with Verification Flows like LEQ, IR/EM, Noise is a plus.Education & ExperienceEducation & ExperienceAdditional RequirementsAdditional RequirementsMore