RELOCATION ASSISTANCE: Relocation assistance may be available

CLEARANCE TYPE: SAP

TRAVEL: No

Description

At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history.

Explore a career engineering what’s possible as a Digital Design Engineer in San Diego, CA.

What You'll Get to Do:

Our Advanced Digital Engineering organization creates the next generation of communications and signal processing systems and will take ideas from concept to working systems aboard the world’s most advanced platforms. We bring design to life in our San Diego labs and have on-site advanced manufacturing just minutes from the beach Southern California is famous.

As a Digital Design Engineer at Northrop Grumman, you will have an opportunity to be a part of an organization that is collaborative, open, transparent, and team-oriented with a focus on team empowerment & shared responsibility, flexibility, continuous learning, and a culture of automation. 

We’re asking: are you ready to challenge the impossible and define possible? If you have hands-on experience in FPGA Development with VHDL, apply today.  

Roles and Responsibilities:

Responsible for research, design, and development for digital designs associated with multi-function software defined radios, as well as automated test equipmentWork with evaluation boards to test proposed designsSupport the implementation of digital FPGA hardware architecture and algorithmsCollaborate with Systems Engineering to ensure firmware design meets system level requirementsReview designs and analysisMay lead a team of Digital VHDL engineers

This position is contingent upon program award and final clearance.

This position may be considered at a higher grade based on the requirements below.

Basic Qualifications Principal Digital Engineer:

Bachelor’s degree in Electrical Engineering or other STEM (Science, Technology, Engineering or Mathematics) discipline with 5 years of digital verification engineering experience using industry standard simulation tools; 3 years with an MS degree; 0 years with PhD.Must have hands on FPGA design experience with VHDL within the past 3 yearsExperience with AMD/Xilinx 7 (Zynq, Kintex and Ultrascale) or Versal family of devices.Experience with Electronic Design Automation (EDA) Tools: Vivado and QuestaSim.Clearance: A final DoD Secret clearance is required to start with ability to obtain higher level clearances. US Citizenship is required in order to obtain and maintain security clearance

Basic Qualifications Senior Principal Digital Engineer

Bachelor’s degree in Electrical Engineering or other STEM (Science, Technology, Engineering or Mathematics) discipline with 9 years of digital verification engineering experience using industry standard simulation tools; 7 years with an MS degree; 4 years with PhD.Must have hands on FPGA design experience with VHDL within the past 3 yearsExperience with AMD/Xilinx 7 (Zynq, Kintex and Ultrascale) or Versal family of devices.Experience with Electronic Design Automation (EDA) Tools: Vivado and QuestaSim.Clearance: A final DoD Secret clearance is required to start with ability to obtain higher level clearances US Citizenship is required in order to obtain and maintain security clearance

Preferred Qualifications Principal and Senior Principal:

Experience with leading and mentoring a team Experience with DSP, MATLAB, and SimuLinkExperience with the Electronic Design Automation (EDA) Tool Quartus.Knowledgeable in FPGA physical constraints and achieving timing closure.Experience with board or system level debug using test equipment such as oscilloscopes and logic analyzers.Generation of Test Benches and support of formal VHDL VerificationActive/Current DoD Secret Clearance or higher level

MSSDEAS

Salary Range: $118,000.00 - $177,000.00Salary Range 2: $146,300.00 - $219,500.00

The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate's experience, education, skills and current market conditions.

Employees may be eligible for a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business.

The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates.

Northrop Grumman is committed to hiring and retaining a diverse workforce. We are proud to be an Equal Opportunity/Affirmative Action Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO/AA and Pay Transparency statement, please visit http://www.northropgrumman.com/EEO. U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.