At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Responsibilities:

Main technical interface between R&D team and tier one customer teams handling resolution of technical issues predominantly in post silicon realm.Primary technical contact for customer SOC and system integration questions.Collaborate with Analog/Digital design, DV teams and Program Management to support customers with ATE deployment, silicon bringup and production ramp.Update R&D teams with the latest customer feedback and support with pre-sales support in a technical capacity.Support customer silicon evaluations and demos.Be voice of the customer and lead initiatives within the team for improvement of collateral to enhance customer experience with the IP.Be able to support onsite bringup for tier 1 customers.

Position Requirements:               

M.S. Electrical/Computer Engineering (or similar degree) and 5 + years of experience or PhD and 1+ Years of relevant experienceExperience working with Memory PHY, Memory Controller and DRAMExperience using advanced mixed signal verification, and system simulation tools.Strong debug and problem-solving skills.Strong background in supporting Post Silicon bringup and debug.Familiarity with advanced technology nodes (7nm and below) is a plus.Must have strong presentation and communication skills.Experience with lab equipment to reproduce customer failures in the lab.

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