R&D Engineering, Principal Engineer
Sypnosis
Analog & Mixed Signal Circuit Design Engineer, Staff
You will be part of an R&D team developing high speed analog and mixed-signal integrated circuits for DDR/LPDDR PHY, High Bandwidth Memory (HBM) PHY, Universal Chiplet Interconnect Express (UCIe) PHY, and Mobile Storage PHY IPs. We are looking for an engineer with theoretical knowledge and practical experience to contribute to the team. You will work with a cross functional design team of analog and digital designers from a wide variety of backgrounds. Our design environment is best-in-class with a full suite of IC design tools, supplemented by custom in-house tools, and supported by an experienced software/CAD team.
Job Responsibilities
Review JEDEC standards to develop analog and mixed-signal sub-block specifications.Identify and refine circuit architectures to achieve optimal power, area, performance and ESD targetsPropose design and verification strategiesOversee physical layout to minimize the effect of parasitic, device stress, process variation, and ESD/Latch-Up protectionPresent simulation data for peer and customer reviewDocument design features and test plansConsult on the electrical characterization of your circuit within the IP productJob Requirements
PhD with 8 years of experience or MSc with 10+ years of analog design experienceIn depth familiarity with transistor level circuit design - sound CMOS design fundamentalsExperience with FinFET technologiesDetailed design experience with at least one, and familiarity with several other DDR or SerDes sub-circuits: receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase mixer, delay-locked loop, phase locked loop, bandgap reference, ADC, DACExperience of ESD protection, ESD network analysis and debug (i.e. circuit techniques, layout for ESD/Latch-UP protection robustness)Familiarity with custom digital design (i.e. high-speed logic paths)Knowledge of design for reliability (i.e. EM, IR, aging, etc.)Knowledge of layout effects (i.e. matching, reliability, proximity effects, etc.)Experience with tools for schematic entry, physical layout, and design verificationHands-on experience with physical layout of high-speed circuits is a plusKnowledge of SPICE simulators and simulation methodsKnowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-captureExperience with TCL, Perl, C, Python, MATLAB, or other scripting languages is desiredGood communication and documentation skillsThe base salary range across the U.S. for this role is between $152,000-$228,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Stay Connected: Join our Talent Community
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
You will be part of an R&D team developing high speed analog and mixed-signal integrated circuits for DDR/LPDDR PHY, High Bandwidth Memory (HBM) PHY, Universal Chiplet Interconnect Express (UCIe) PHY, and Mobile Storage PHY IPs. We are looking for an engineer with theoretical knowledge and practical experience to contribute to the team. You will work with a cross functional design team of analog and digital designers from a wide variety of backgrounds. Our design environment is best-in-class with a full suite of IC design tools, supplemented by custom in-house tools, and supported by an experienced software/CAD team.
Job Responsibilities
Review JEDEC standards to develop analog and mixed-signal sub-block specifications.Identify and refine circuit architectures to achieve optimal power, area, performance and ESD targetsPropose design and verification strategiesOversee physical layout to minimize the effect of parasitic, device stress, process variation, and ESD/Latch-Up protectionPresent simulation data for peer and customer reviewDocument design features and test plansConsult on the electrical characterization of your circuit within the IP productJob Requirements
PhD with 8 years of experience or MSc with 10+ years of analog design experienceIn depth familiarity with transistor level circuit design - sound CMOS design fundamentalsExperience with FinFET technologiesDetailed design experience with at least one, and familiarity with several other DDR or SerDes sub-circuits: receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase mixer, delay-locked loop, phase locked loop, bandgap reference, ADC, DACExperience of ESD protection, ESD network analysis and debug (i.e. circuit techniques, layout for ESD/Latch-UP protection robustness)Familiarity with custom digital design (i.e. high-speed logic paths)Knowledge of design for reliability (i.e. EM, IR, aging, etc.)Knowledge of layout effects (i.e. matching, reliability, proximity effects, etc.)Experience with tools for schematic entry, physical layout, and design verificationHands-on experience with physical layout of high-speed circuits is a plusKnowledge of SPICE simulators and simulation methodsKnowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-captureExperience with TCL, Perl, C, Python, MATLAB, or other scripting languages is desiredGood communication and documentation skillsThe base salary range across the U.S. for this role is between $152,000-$228,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Stay Connected: Join our Talent Community
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
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