Company:Qualcomm India Private Limited

Job Area:Engineering Group, Engineering Group > Hardware Engineering

General Summary:

8-12 years of work experience in ASIC IP cores design

Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering

Knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB/PCIE/Ethernet preferred.

Work closely with the SoC verification and validation teams for pre/post Silicon debug

Hands on experience in Low power design is required

Hands on experience in Multi Clock designs, Asynchronous interface is a must.

Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.

Understanding of constraint development and timing closure is a plus.

Experience in Synthesis / Understanding of timing concepts is a plus.

Strong experience in micro architecting RTL design from high level design specification.

Excellent problem solving skills, strong communication and team work skills are mandatory.

Self-driven, needs to work with minimum supervision.

Experience in System Verilog, Verilog, C/C++, Perl and Python is a plus

Ability to lead a small design team

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

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