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Life at IntelDiversity at IntelThe Central Device Modeling Group under Intel's Technology Development organization is looking for an intern to support modeling characterization work. The duration of this work can be 6-12month depending on the candidate's availability. This position requires the candidate to be full time physically in the lab.
As a semiconductor device modeling intern, you will
Develop DC/CV measurement routines, and collect data for modeling purpose under supervision and guidance from Senior members in the team. Develop RF(s-parameter) measurement routines, and collect RF data for modeling purpose under supervision and guidance from Senior members in the team. Get trained on our Finfet technology, devices and modeling aspects. Work together with other talents in the team on technical solutions.This internship is slated to start January and March of 2025 and run 6-12 months, full-time.
In addition, candidate should have effective verbal/written communication and analytical problem solving and troubleshooting skills. The person should enjoy working in a fast-paced environment where adaptability and flexibility is key to their success. Having depth and breadth of knowledge of managing servers in a large-scale distributed environment is a core competency of this individual.
QualificationsMinimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
What we need to see (Minimum Qualifications):
A Bachelor's degree in electrical engineering or related discipline. Currently a Master or PHD student in electrical engineering or related discipline.At least 1 course in semiconductor device physics or similar course.At least 3 months of hands-on experience in semiconductor device DC/CV on-wafer characterization bench testing, tools, and techniques.At least 3 months of experience in RF/noise tests.At least 3 months of hands-on experience in Python or C, Shell programming.Preferred Qualifications:
Previous intern experience in the semiconductor industry experience.Coursework or experience in semiconductor process flow, device layout and simple circuit operation.Experience in finfet technologies. Understanding of layout effects and models. Experienced in a Cadence design environment, including schematic capture, virtuoso layout design, DRC, LVS, and layout extractions.The ability to debug issues and data independently.Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Annual Salary Range for jobs which could be performed in the US $63,000.00-$166,000.00
*Salary range dependent on a number of factors including location and experienceWorking ModelThis role will require an on-site presence.* Job posting details (such as work model, location or time type) are subject to change.