Cadence Solutions (North America) team is looking for an experienced RTL designer to contribute to architecture and design for next generation SoCs targeting Hyper-Scalar, Automotive, IoT and Mil-Aero markets.
Position presents a learning and growth opportunity for candidate to develop into an architect (System) in the future.
Responsibilities:
CPU IP selection/configuration/integration for ARM and/or RISCV CPU and System IPDesign IP selection/configuration/integration for Memory and/or Interface IP (PCIe, Ethernet, USB and other)Digital design and IP creation/ownership from High Level Arch SpecificationCreate detailed Micro-architecture specification, work closely with the architectUnderstanding of performance measurement and refinement. Ability to work with verification/validation team to create performance verification planRTL developmentSupport Verification teams. Support test bench development, review verification and vPlans. Provide timely specification clarifications and debug supportPhysical design deliverables. Create functional timing constraints, synthesize RTL to ensure power and area targets are met and constraints are correctPlan development schedule in detail and track deliverables to ensure timely IP delivery to all consumersWork with multi-disciplinary teams to ensure design block/IP success for all target specifications in SiliconQualifications:
10+ years of Front End design and/or verification.with a BS/MS Engineering or Computer Sciences
Rich experience in IP creation and/or SoC and IP (CPU, Memory, Interface) integration
Expert in RTL design (Verilog), simulators debuggers
Hands on Experience in Synthesis, SDC creation and support PD and STA teams.
Hands on experience on CDC/RDC setup, cleanup and ownership.
Experience in C/C++ and/or Python (or scripting language)
Experience in driving results in multi-disciplinary organization
Desirable:
A Self-motivated person with good communication and design management skills
Experience with Cadence front end toolset
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