Organization & Role

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!
 

Teradyne’s Silicon Technology Engineering (STE) Digital ASIC Group is responsible for developing advanced node ASICs for Teradyne’s next-generation products, such as SOC and Memory Test Instruments. Teradyne’s products must be ahead of the semiconductor industry for our customers to ship production chips/products.

You will join a best-in-class ASIC team as a Verification Engineer working in collaboration with Digital & Analog designers and product architects to develop Teradyne’s next-generation large Mixed Signal ASICs. You will be involved in all phases of development, including specification, architecture, design, verification, and silicon bring-up, focusing on developing UVM-based SystemVerilog Reference Models.

Responsibilities

In this role you will be responsible for:

Being a major contributor Architecting and developing reusable verification environment Architecting and developing reference models for Device Under Test Developing detailed executable test plans Developing IUVCs, tests, and assertions Porting tests from simulation to lab
  Leading IP, ASIC or FPGA verification projects Developing verification schedules for complex projects Managing project execution, from planning to the tapeout sign-off Defining verification strategy and methodology Mentoring junior engineers Making verification IP selections Basic Qualifications & Skills 10+ years of digital verification experience with a good understanding of digital design Proven track record of project execution ownership Extensive experience modeling Transaction level SystemVerilog Reference Models Extensive experience with SystemVerilog programming Extensive experience with UVM and Coverage Driven Methodology Experience with Assertion Based Verification Experience with Cadence tools (Xcelium, vManager) is a plus Experience with gate-level simulations is a plus. Experience with C/C++ is a plus Experience with PCIe, AXI, LPDDR5 protocols is a plus. Knowledge of Make, Python, and Regular Expressions is a plus. Lab validation experience is a plus

 

Education

BS or MSEE

 

 

 

 

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