SummaryPosted: Nov 20, 2024Role Number:200579851We are seeking experienced Analog Mixed-Signal designers to join our high-speed SerDes team. Our team specializes in building next generation high-performance wireline transceivers delivering intellectual-property (IP) for Apple’s world-leading system-on-chip (SOC)! In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to create state-of-the-art IPs key to Apple’s products. You will be challenged to make the best-in-class designs to surprise and delight Apple customers. With transforming the user experience in focus, you will get an opportunity to work on designs which makes the best systems. This enables you to learn to end-to-end system while exceeding the highest expectations of quality, innovation and efficiency. If you have strong fundamentals and a track record of tackling technical challenges, If you are passionate about learning new skills and improving the value of your work, If you like to be tuned to the bigger-picture while diving deeply into the details to innovate and solve problems, We invite you to join and grow with our team!DescriptionDescriptionWe work on the development of high-performance and high-speed AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, high-speed clock generation and low-jitter distribution, phase interpolator, DLL, VCO, LDO) with best in class power, performance, and area (PPA). We lead discussions with multi-functional teams (e.g., architecture, SIPI, packaging, board design, DFT, ESD) to create and drive block-level specifications, mixed-signal implementations and behavioral modeling. We work closely with SOC teams to deliver IP views and ensure they meet the quality standards. While developing these complex IPs on regular basis, we interact with peers/management to communicate progress, discuss new ideas and drive new implementations/concepts making it an exciting and growth-oriented work environment.Minimum QualificationsMinimum QualificationsBSEE requiredKey QualificationsKey QualificationsPreferred QualificationsPreferred QualificationsThe ideal candidate should have deep understanding of AMS design with experience in high-speed serial links.Solid understanding of designing AMS circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, FiltersUnderstanding of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniquesDeep understanding and experience with digitally assisted analog design concepts (e.g. background calibrations, LMS based adaptive loops)Proven experience working on system and architecture teams to drive block-level and IP requirementsProven track record working with large teams and guiding junior engineersExperience with high speed digital circuits (e.g., serializer, deserializer, counters, dividers, etc.) with solid understanding of digital design conceptsExperience and proven understanding of Tx/Rx equalization techniques and circuits (e.g. CTLE, DFE, de-emphasis) for 20+ Gbps NRZ and PAM applicationsExperience with EQ adaptation methods and circuit interactions to improve PPASolid understanding of CDR architectures and implementationsExperience in Analog Mixed Signal circuit modeling and performance evaluation (e.g. SystemVerilog, Matlab, Python, VerilogAMS)Hands-on experience to drive lab testing, debug and data analysisHands-on experience in advanced CMOS technologies, design with FinFet technologyHands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterizationEXPERIENCE IN THE FOLLOWING AREAS IS A PLUSConcepts of timing closure and related industry tools (e.g., Nanotime, Primetime)Concepts of IP delivery and quality checksKnowledge of common high-speed SerDes protocols (e.g., PCIe, USB, DP, MPHY) is helpfulSkills in scripting and automation to improve efficiency are highly desirableEducation & ExperienceEducation & ExperienceAdditional RequirementsAdditional RequirementsMore

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